Patents by Inventor Ikuya TERAUCHI

Ikuya TERAUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240234326
    Abstract: A wiring substrate includes first conductor pads formed on a surface of an insulating layer, second conductor pads formed on the surface of the insulating layer, a second insulating layer covering the surface of the insulating layer and first and second conductor pads, first via conductors formed in first via holes penetrating through the second insulating layer such that the first via conductors are formed on the first conductor pads, and second via conductors formed in second via holes penetrating through the second insulating layer such that the second via conductors are formed on the second conductor pads. The first and second conductor pads are formed such that an annular width amount of each second conductor pad is smaller than an annular width amount of each first conductor pad and that a haloing amount in each second conductor pad is smaller than a haloing amount in each first conductor pad.
    Type: Application
    Filed: October 19, 2023
    Publication date: July 11, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Ikuya TERAUCHI, Shogo FUKUI, Ryo ANDO, Keisuke SHIMIZU
  • Publication number: 20240237231
    Abstract: A method for manufacturing a wiring substrate includes forming first conductor pads and second conductor pads having a shorter inter-pad distance than the first conductor pads, forming a second insulating layer covering the first conductor pads and the second conductor pads, forming first via holes exposing the first conductor pads, applying a first desmear treatment such that residues are removed from the first via holes, forming second via holes in the second insulating layer after the first desmear treatment such that the second via holes expose the second conductor pads, applying a second desmear treatment such that residues are removed from the second via holes, forming first via conductors in the first via holes such that the first via conductors are formed on the first conductor pads, and forming second via conductors in the second via holes such that the second via conductor are formed on the second conductor pads.
    Type: Application
    Filed: October 19, 2023
    Publication date: July 11, 2024
    Applicant: IBIDEN CO., LTD.
    Inventor: Ikuya TERAUCHI
  • Publication number: 20240136294
    Abstract: A wiring substrate includes first conductor pads formed on a surface of an insulating layer, second conductor pads formed on the surface of the insulating layer, a second insulating layer covering the surface of the insulating layer and first and second conductor pads, first via conductors formed in first via holes penetrating through the second insulating layer such that the first via conductors are formed on the first conductor pads, and second via conductors formed in second via holes penetrating through the second insulating layer such that the second via conductors are formed on the second conductor pads. The first and second conductor pads are formed such that an annular width amount of each second conductor pad is smaller than an annular width amount of each first conductor pad and that a haloing amount in each second conductor pad is smaller than a haloing amount in each first conductor pad.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 25, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Ikuya TERAUCHI, Shogo FUKUI, Ryo ANDO, Keisuke SHIMIZU
  • Publication number: 20240138076
    Abstract: A method for manufacturing a wiring substrate includes forming first conductor pads and second conductor pads having a shorter inter-pad distance than the first conductor pads, forming a second insulating layer covering the first conductor pads and the second conductor pads, forming first via holes exposing the first conductor pads, applying a first desmear treatment such that residues are removed from the first via holes, forming second via holes in the second insulating layer after the first desmear treatment such that the second via holes expose the second conductor pads, applying a second desmear treatment such that residues are removed from the second via holes, forming first via conductors in the first via holes such that the first via conductors are formed on the first conductor pads, and forming second via conductors in the second via holes such that the second via conductor are formed on the second conductor pads.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 25, 2024
    Applicant: IBIDEN CO., LTD.
    Inventor: Ikuya TERAUCHI
  • Publication number: 20230403789
    Abstract: A wiring substrate includes an insulating layer, and a conductor layer including a wiring formed on the insulating layer. The wiring in the conductor layer has a first section and a second section formed such that a wiring width in the second section is smaller than a wiring width in the first section and that a wiring thickness in the second section is larger than a wiring thickness in the first section.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 14, 2023
    Applicant: IBIDEN CO., LTD.
    Inventors: Hiroki WAKAMORI, Ikuya TERAUCHI, Takahiro YAMADA
  • Publication number: 20220192018
    Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on the insulating layer and including a conductor pad having a rectangular planar shape, and a solder resist layer formed on the insulating layer such that the solder resist layer is covering the conductor layer formed on the insulating layer. The solder resist layer has an opening formed such that the opening is exposing 50% or more of an area of a surface of the conductor pad on the opposite side with respect to the insulating layer and exposing a side surface and the surface of the conductor pad at side portions of a peripheral edge of the conductor pad and that the solder resist layer is covering the side surface and the surface of the conductor pad at one or more of corner portions of the peripheral edge of the conductor pad.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 16, 2022
    Applicant: IBIDEN CO., LTD.
    Inventors: Shunsuke SAKAI, Shuto IWATA, Ikuya TERAUCHI, Takahiro YAMADA
  • Patent number: 10856415
    Abstract: A printed wiring board includes a conductor layer including first and second pads, a coating layer covering the conductor layer and having first opening exposing the first pad and second opening exposing the second pad, and metal bumps including a first bump on the first pad and a second bump on the second pad such that the first and second bumps protrude from the coating layer. The first and second openings are formed such that diameter of the second pad is smaller than diameter of the first pad. The first and second bumps are formed such that height of protruding portion of the first bump from the surface of the coating layer is substantially equal to height of protruding portion of the second bump from the surface of the coating layer and that the second bump covers an area of the coating layer on the surface surrounding the second opening.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 1, 2020
    Assignee: IBIDEN CO., LTD.
    Inventor: Ikuya Terauchi
  • Publication number: 20200163214
    Abstract: A printed wiring board includes a conductor layer including first and second pads, a coating layer covering the conductor layer and having first opening exposing the first pad and second opening exposing the second pad, and metal bumps including a first bump on the first pad and a second bump on the second pad such that the first and second bumps protrude from the coating layer. The first and second openings are formed such that diameter of the second pad is smaller than diameter of the first pad. The first and second bumps are formed such that height of protruding portion of the first bump from the surface of the coating layer is substantially equal to height of protruding portion of the second bump from the surface of the coating layer and that the second bump covers an area of the coating layer on the surface surrounding the second opening.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 21, 2020
    Applicant: IBIDEN CO., LTD.
    Inventor: Ikuya TERAUCHI