Patents by Inventor Ilie G. Tanase

Ilie G. Tanase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10956499
    Abstract: A data storage and retrieval system for a computer memory includes a stream graph engine extracting graph data from streaming data, the graph data occupying a sliding window and comprising a plurality of slices representing a set of contiguous graphs, and where each slice of the plurality of slices corresponds to a given graph structure and its properties at a particular time, the stream graph engine causing the computer memory to store an on-disk portion of the graph data including a key table, a timestamp table and a plurality of property files, wherein the key table comprises a plurality of pointers to corresponding entries of the timestamp table, wherein each of the entries of the timestamp table comprise a corresponding timestamp and a pointer to the properties files, wherein the properties files comprise properties of a corresponding graph of the set of contiguous graphs, an in-memory portion of the graph data having a cache data structure storing a subset of the key table, and a versioning control modu
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ching-Yung Lin, Yanbin Liu, Lifeng Nai, Wei Tan, Ilie G. Tanase, Yinglong Xia
  • Patent number: 10552450
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Publication number: 20190384774
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Application
    Filed: August 27, 2019
    Publication date: December 19, 2019
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Publication number: 20190294634
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Publication number: 20190278807
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Patent number: 10394891
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Patent number: 10380188
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Publication number: 20190012258
    Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.
    Type: Application
    Filed: August 28, 2018
    Publication date: January 10, 2019
    Inventors: Gheorghe Almasi, Barnaby Dalton, Ilie G. Tanase, Ettore Tiotto
  • Patent number: 10108540
    Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gheorghe Almasi, Barnaby Dalton, Ilie G. Tanase, Ettore Tiotto
  • Patent number: 10108539
    Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gheorghe Almasi, Barnaby Dalton, Ilie G. Tanase, Ettore Tiotto
  • Publication number: 20180075159
    Abstract: A data storage and retrieval system for a computer memory includes a stream graph engine extracting graph data from streaming data, the graph data occupying a sliding window and comprising a plurality of slices representing a set of contiguous graphs, and where each slice of the plurality of slices corresponds to a given graph structure and its properties at a particular time, the stream graph engine causing the computer memory to store an on-disk portion of the graph data including a key table, a timestamp table and a plurality of property files, wherein the key table comprises a plurality of pointers to corresponding entries of the timestamp table, wherein each of the entries of the timestamp table comprise a corresponding timestamp and a pointer to the properties files, wherein the properties files comprise properties of a corresponding graph of the set of contiguous graphs, an in-memory portion of the graph data having a cache data structure storing a subset of the key table, and a versioning control modu
    Type: Application
    Filed: September 13, 2016
    Publication date: March 15, 2018
    Inventors: CHING-YUNG LIN, YANBIN LIU, LIFENG NAI, WEI TAN, ILIE G. TANASE, YINGLONG XIA
  • Publication number: 20180039673
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Publication number: 20180039709
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Publication number: 20180039710
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Publication number: 20160147536
    Abstract: Techniques for switching between two (thread and lane) modes of execution in a dual execution mode processor are provided. In one aspect, a method for executing a single instruction stream having alternating serial regions and parallel regions in a same processor is provided. The method includes the steps of: creating a processor architecture having, for each architected thread of the single instruction stream, one set of thread registers, and N sets of lane registers across N lanes; executing instructions in the serial regions of the single instruction stream in a thread mode against the thread registers; executing instructions in the parallel regions of the single instruction stream in a lane mode against the lane registers; and transitioning execution of the single instruction stream from the thread mode to the lane mode or from the lane mode to the thread mode.
    Type: Application
    Filed: November 24, 2014
    Publication date: May 26, 2016
    Inventors: David J. Edelsohn, Jose E. Moreira, Mauricio J. Serrano, Ilie G. Tanase, Jessica H. Tseng, Peng Wu
  • Publication number: 20160147537
    Abstract: Techniques for switching between two (thread and lane) modes of execution in a dual execution mode processor are provided. In one aspect, a method for executing a single instruction stream having alternating serial regions and parallel regions in a same processor is provided. The method includes the steps of: creating a processor architecture having, for each architected thread of the single instruction stream, one set of thread registers, and N sets of lane registers across N lanes; executing instructions in the serial regions of the single instruction stream in a thread mode against the thread registers; executing instructions in the parallel regions of the single instruction stream in a lane mode against the lane registers; and transitioning execution of the single instruction stream from the thread mode to the lane mode or from the lane mode to the thread mode.
    Type: Application
    Filed: September 30, 2015
    Publication date: May 26, 2016
    Inventors: David J. Edelsohn, Jose E. Moreira, Mauricio J. Serrano, Ilie G. Tanase, Jessica H. Tseng, Peng Wu
  • Patent number: 8959528
    Abstract: Acknowledging incoming messages, including: determining, by an acknowledgement dispatching module, whether an incoming message has been received in an active message queue; responsive to determining that the incoming message has been received in the active message queue, resetting, by the acknowledgement dispatching module, an acknowledgment iteration counter; incrementing, by the acknowledgement dispatching module, the acknowledgment iteration counter; determining, by the acknowledgement dispatching module, whether the acknowledgment iteration counter has reached a predetermined threshold; and responsive to determining that the acknowledgment iteration counter has reached the predetermined threshold, processing, by the acknowledgement dispatching module, all messages in the active message queue.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tsai-Yang Jea, Serban C. Maerean, Ilie G. Tanase, Hanhong Xue
  • Patent number: 8954991
    Abstract: Acknowledging incoming messages, including: determining, by an acknowledgement dispatching module, whether an incoming message has been received in an active message queue; responsive to determining that the incoming message has been received in the active message queue, resetting, by the acknowledgement dispatching module, an acknowledgment iteration counter; incrementing, by the acknowledgement dispatching module, the acknowledgment iteration counter; determining, by the acknowledgement dispatching module, whether the acknowledgment iteration counter has reached a predetermined threshold; and responsive to determining that the acknowledgment iteration counter has reached the predetermined threshold, processing, by the acknowledgement dispatching module, all messages in the active message queue.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tsai-Yang Jea, Serban C. Maerean, Ilie G. Tanase, Hanhong Xue
  • Publication number: 20140372725
    Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gheorghe Almasi, Barnaby Dalton, Ilie G. Tanase, Ettore Tiotto
  • Publication number: 20140372724
    Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gheorghe Almasi, Barnaby Dalton, Ilie G. Tanase, Ettore Tiotto