Abstract: A basic single-chip building block for a RS decoder system is partitioned into a plurality of sections the first of which consists of a plurality of syndrome subcells each of which contains identical standard-basis finite-field multipliers that are programmable between 10-bit and 8-bit operation. A desired number of basic building blocks may be assembled to provide a RS decoder of any syndrome subcell size that is programmable between 10-bit and 8-bit operation.

Abstract: A concatenated coding system consisting of a (255,223) Reed-Solomon outer code and a convolutional inner code is provided with either a block of preinterleaved frames or an interleaver of frames in a block of data symbols to be coded in the outer decoder. By interleaving, errors are constrained to occur in only one symbol in a frame, which can be corrected by the Reed-Solomon outer decoder. After transmission and inner decoding, the data symbols are deinterleaved for outer decoding. Instead of preinterleaving at the source, or interleaving before inner encoding, the frames of data symbols may be interleaved at the receiver after inner decoding and then combined with the inner decoded check symbols for outer decoding. The outer encoder is a bit-serial Reed-Solomon encoder with programmable interleaving, and the inner decoder is a Viterbi decoder.

Abstract: Two pipeline (255,233) RS decoders, one a time domain decoder and the other a transform domain decoder, use the same first part to develop an errata locator polynomial .tau.(x), and an errata evaluator polynominal A(x). Both the time domain decoder and transform domain decoder have a modified GCD that uses an input multiplexer and an output demultiplexer to reduce the number of GCD cells required. The time domain decoder uses a Chien search and polynomial evaluator on the GCD outputs .tau.(x) and A(x), for the final decoding steps, while the transform domain decoder uses a transform error pattern algorithm operating on .tau.(x) and the initial syndrome computation S(x), followed by an inverse transform algorithm in sequence for the final decoding steps prior to adding the received RS coded message to produce a decoded output message.

Abstract: A pipeline binary updown counter is comprised of simple stages that may be readily replicated. Each stage is defined by the Boolean logic equationA.sub.n (t)=A.sub.n (t-1).sym.[(U.multidot.P.sub.n)+(D.multidot.Q.sub.n)]where A.sub.n (t) denotes the value of the nth bit at time t. The input to the counter has three values represented by two binary signals U and D such that if both are zero, the input is zero, if U=0 and D=1, the input is -1 and if U=1 and D=0, the input is +1. P.sub.n represents a product of A.sub.k 's for 1.ltoreq.k.ltoreq.-1, while Q.sub.n represents the product of A's for 1.ltoreq.k.ltoreq.n-1, where A.sub.k is the complement of A.sub.k and P.sub.n and Q.sub.n are expressed as the following two equationsP.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1Q.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1which can be written in recursion form asP.sub.n =P.sub.n-1 .multidot.A.sub.n-1Q.sub.n =Q.sub.n-1 .multidot.A.sub.n-1with the initial values P.sub.1 =1 and Q.sub.1 =1.