Patents by Inventor Indira Seshadri

Indira Seshadri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200279956
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Indira SESHADRI, Ekmini Anuja DE SILVA, Jing GUO, Ruqiang BAO, Muthumanickam SANKARAPANDIAN, Nelson FELIX
  • Publication number: 20200279913
    Abstract: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: Mona A. Ebrish, Fee Li Lie, Nicolas Loubet, Gauri Karve, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger
  • Publication number: 20200266100
    Abstract: Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Nicole Saulnier, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie, Isabel Cristina Chu, Hosadurga Shobha, Ekmini A. De Silva
  • Patent number: 10741454
    Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing Guo, Ekmini A. De Silva, Nicolas Loubet, Indira Seshadri, Nelson Felix
  • Patent number: 10741452
    Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric R. Miller, Stuart A. Sieg, Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz
  • Patent number: 10734523
    Abstract: A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fee Li Lie, Mona Ebrish, Ekmini A. De Silva, Indira Seshadri, Gauri Karve, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Nicolas Loubet
  • Patent number: 10734234
    Abstract: The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kisup Chung, Ekmini Anuja De Silva, Andrew Greene, Siva Kanakasabapathy, Indira Seshadri
  • Patent number: 10699912
    Abstract: A computer program product and methods are provided for semiconductor processing. The method includes forming a masking layer on a first region. The method also includes implanting a second region. The method further includes depositing a protective layer over the first region and the second region, with the protective layer being selectively etchable to the masking layer and thicker over the second region. The additional includes removing the protective layer from the first region. The method also includes etching the masking layer exposing a bottom layer. The method further includes removing the protective layer from the second region and the bottom layer from the first region.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Indira Seshadri, Ekmini A. De Silva
  • Patent number: 10678135
    Abstract: A surface treatment composition and methods for improving adhesion of an organic layer on a titanium-containing hardmask includes forming a self-assembled monolayer on a surface of the titanium-containing hardmask prior to depositing the organic layer. The self-assembled monolayer is formed from a blend of alkyl phosphonic acids of formula (I): X(CH2)nPOOH2 (I), wherein n is 6 to 16 and X is either CH3 or COOH, wherein a ratio of the methyl terminated (CH3) alkyl phosphonic acid to the carboxyl terminated (COOH) alkyl phosphonic acid ranges from 25:75 to 75:25.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekmini A. De Silva, Dario Goldfarb, Indira Seshadri
  • Patent number: 10665715
    Abstract: A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praveen Joseph, Indira Seshadri, Ekmini A. De Silva, Stuart A. Sieg
  • Patent number: 10665461
    Abstract: A method for fabricating a semiconductor device with multiple threshold voltages includes masking a substrate structure to selectively form work-function metal layers on vertical field effect transistors. In the method, a first work function metal layer is formed on a high-k dielectric layer of a substrate structure comprising vertical field effect transistors. The first work function metal layer and the high-k dielectric layer are etched to form gate regions for each vertical field effect transistor. A resist mask is formed over a first of the vertical field effect transistors. The resist mask isolates the first of the vertical field effect transistors from a second of the vertical field effect transistors. A second work function metal layer is selectively formed on the first work function metal layer of the gate region of the second of the vertical field effect transistors. The resist mask is then removed.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praveen Joseph, Indira Seshadri, Ekmini Anuja De Silva
  • Patent number: 10656527
    Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack more particularly includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on the resist layer, the selective deposition of the metal-containing layer on the resist layer occurring after pattern development. The method further includes exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, and selectively depositing the metal-containing layer on the developed pattern in the resist layer. The selective deposition avoids deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ekmini Anuja De Silva, Indira Seshadri, Jing Guo, Ashim Dutta, Nelson Felix
  • Patent number: 10658521
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Indira Seshadri, Ekmini Anuja De Silva, Jing Guo, Ruqiang Bao, Muthumanickam Sankarapandian, Nelson Felix
  • Publication number: 20200135484
    Abstract: Methods for forming semiconductor fins include forming a protective layer around a base of a hardmask fin on an underlying semiconductor layer. A portion of the hardmask fin is etched away with an etch that is selective to the protective layer. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.
    Type: Application
    Filed: October 29, 2018
    Publication date: April 30, 2020
    Inventors: Eric R. Miller, Stuart A. Sieg, Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz
  • Publication number: 20200135570
    Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.
    Type: Application
    Filed: October 29, 2018
    Publication date: April 30, 2020
    Inventors: Eric R. Miller, Stuart A. Sieg, Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz
  • Patent number: 10629489
    Abstract: A method of preventing the collapse of fin structures is provided. The method includes forming a plurality of vertical fins on a substrate, and a hard mask stack on each of the vertical fins. The method further includes forming a cover layer on the plurality of vertical fins and hard mask stacks, and reducing the height of the cover layer to expose an upper portion of each of the hard mask stacks. The method further includes forming a bracing layer on the reduced height cover layer and exposed portion of each of the hard mask stacks, and removing a portion of the bracing layer to expose a portion of the reduced height cover layer and form a bracing segment on the exposed portion of each of the hard mask stacks. The method further includes removing the reduced height cover layer.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Indira Seshadri, Stuart A. Sieg, Praveen Joseph, Ekmini A. De Silva
  • Patent number: 10629495
    Abstract: A semiconductor structure comprises a semiconductor substrate, an N-type stacked nanosheet channel structure formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures comprises a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer, and with the gate work function metal layer being separated from the channel regions by the gate dielectric layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Indira Seshadri, Ekmini Anuja De Silva, Jing Guo, Romain J. Lallement, Ruqiang Bao, Zhenxing Bi, Sivananda Kanakasabapathy
  • Publication number: 20200118831
    Abstract: A computer program product and methods are provided for semiconductor processing. The method includes forming a masking layer on a first region. The method also includes implanting a second region. The method further includes depositing a protective layer over the first region and the second region, with the protective layer being selectively etchable to the masking layer and thicker over the second region. The additional includes removing the protective layer from the first region. The method also includes etching the masking layer exposing a bottom layer. The method further includes removing the protective layer from the second region and the bottom layer from the first region.
    Type: Application
    Filed: October 12, 2018
    Publication date: April 16, 2020
    Inventors: Indira Seshadri, Ekmini A. De Silva
  • Patent number: 10622248
    Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekmini A. De Silva, Nelson Felix, Indira Seshadri, Stuart A. Sieg
  • Patent number: 10622250
    Abstract: Apparatus and methods for dielectric gap fill evaluations are provided. In one example, a method can comprise providing a gap fill substrate over one or more interlayer dielectric trenches of a dielectric layer and over a first material located in the one or more interlayer dielectric trenches. The method can also comprise depositing a gap fill candidate material within one or more gap fill substrate trenches of the gap fill substrate. Furthermore, the method can comprise etching the gap fill candidate material until a void within the first material is identified. Additionally, the method can comprise filling the one or more gap fill substrate trenches with a second material to form one or more contacts with the first material to measure a leakage current of one or more pitches.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Ekmini Anuja De Silva, Gauri Karve, Fee Li Lie, Nicole Adelle Saulnier, Indira Seshadri, Hosadurga Shobha