Abstract: A circuit is presented including a plurality of cells separated by a plurality of cell boundaries and at least one curved gate cut region disposed over a curved cell boundary of the plurality of cell boundaries. The at least one curved gate cut region separates a reduced active area from a widened active area. The reduced active area is defined above the curved cell boundary and the widened active area is defined below the curved cell boundary.

Abstract: A semiconductor device is provided. The semiconductor device includes a bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer, the gate stack including a work function metal (WFM) layer, a channel fin formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed in a gate landing area over the gate stack, a second ILD layer formed in an area other than the gate landing area, and a WFM encapsulation layer formed between the first ILD layer and the second ILD layer, and formed on sidewalls of the gate stack.

Abstract: An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.

Abstract: A semiconductor device is provided. The semiconductor device includes an interlayer dielectric layer; and a plurality of metal contacts formed in the interlayer dielectric layer. The plurality of metal contacts include a plurality of shallow metal contacts having a first depth, and a plurality of deep metal contacts having a second depth that is greater than the first depth, wherein a first one of the shallow metal contacts overlaps and directly contacts a first one of the deep metal contacts, and wherein the plurality of metal contacts have an equal spacing therebetween.

Abstract: A method of forming a transistor structure is provided. The method includes forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region, depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels, respectively, conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region and depositing and anisotropically etching back the first spacer material in the space with enough cycles to fill the space to form a third spacer.

Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Abstract: A method includes forming a first semiconducting channel comprising a plurality of vertical nanowires and a second semiconducting channel comprising a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are formed in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are formed in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.

Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

Abstract: A method of forming a transistor structure is provided. The method includes forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region, depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels, respectively, conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region and depositing and anisotropically etching back the first spacer material in the space with enough cycles to fill the space to form a third spacer.

Abstract: An apparatus including a substrate and a first nanosheet device located on the substrate. A second nanosheet device is located on the substrate, where the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device and the at least one first gate has a first width. At least one second gate located on the second nanosheet device and the at least one second gate has a second width. The first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device. The diffusion break prevents the first nanosheet device from contacting the second nanosheet device, and the diffusion break has a third width. The third width is larger than the first width and the second width.

Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

Abstract: A method of forming a semiconductor structure includes forming a first array of mandrels on a hardmask layer disposed on an uppermost surface of a semiconductor substrate. First sidewall image transfer spacers are formed on opposing longitudinal sidewalls of each mandrel in the first array of mandrels. A second array of mandrels is formed on the hardmask layer. Each mandrel in the second array of mandrels is laterally separated from each mandrel in the first array of mandrels by the first sidewall image transfer spacers. Second sidewall image transfer spacers are formed on opposing transversal sidewalls of the first array of mandrels and the second array of mandrels. Portions of the second sidewall image transfer spacers are selectively removed to define a crosslink fin pattern to be transferred to the semiconductor substrate.

Abstract: A method for forming a planarization layer is provided that can include depositing an organic planarization layer on a deposition surface using a spin on deposition method; and treating the deposited organic planarization layer with a solvent anneal. In some embodiments, a vapor of solvent is passed over the deposited organic planarization layer to increase uniformity of the deposited organic planarization layer. The method may further include curing the deposited organic planarization layer with a thermal anneal.

Abstract: An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.

Abstract: The embodiments herein describe a crossbar VFET where the crossbar channel (or fin) that extends between a pair of channels (fins) has reduced corner rounding, or no corner rounding. This can be achieved by developing a masking feature before etching the channels in the VFET that results in reduced, or no corner rounding in the channel structure etched using the masking feature.

Abstract: Embodiments of the invention include a dielectric reflow technique for boundary control in which a first layer is deposited on a first transistor region and a second transistor region, the first and second transistor regions being adjacent. A dielectric layer is formed to protect the second transistor region such that the first transistor region is exposed, the dielectric layer bounded at a first location. In response to removing a portion of the first layer on the first transistor region, the dielectric layer protecting the second transistor region is reflowed such that at least a reflowed portion of the dielectric layer extends beyond the first location.

Abstract: A method is presented for constructing a semiconductor device. The method includes forming a plurality of fins over a nanosheet stack and a substrate, forming spacers between the nanosheet stack and one or more of the plurality of fins, each spacer defining a different shape, forming gate spacers adjacent the plurality of fins, the gate spacers directly contacting the one or more of the plurality of fins having a spacer, forming a barrier spacer between a set of fins of the plurality of fins, the barrier spacer directly contacting a top surface of a shallow trench isolation (STI) region, forming n-type epitaxial regions between the plurality of fins, forming p-type epitaxy regions over the n-type epitaxial regions, and forming a first contact extending vertically through the semiconductor device adjacent the barrier spacer and extending laterally away from the barrier spacer to directly contact a sidewall of an n-type epitaxial region.

Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first, via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.

Abstract: An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.