Abstract: A method for making capacitor-over-bit line (COB) DRAM using a self-aligned contact etching technology is achieved. After forming FET gate electrodes, sidewall spacers are formed from a first Si.sub.3 N.sub.4 etch-stop layer, while a portion of the Si.sub.3 N.sub.4 is retained as an etch-stop layer on the source/drain areas. Self-aligned contact openings are etched in a first oxide layer to the source/drain areas, and polysilicon landing plugs are formed in all the self-aligned openings. A second oxide layer is deposited and contact holes are etched to the landing plugs for bit lines. A polycide layer having a cap layer is deposited and patterned to form bit lines. A third Si.sub.3 N.sub.4 etch-stop layer is conformally deposited over the bit lines and patterned to form openings over the landing plugs for the capacitor node contacts while forming Si.sub.3 N.sub.4 sidewall spacers on the bit lines exposed in the openings.

Abstract: A process for fabricating a DRAM cell has been developed, in which two interlaced patterns, each comprised of capacitor node contact holes and bit line contact holes, are independently created, each using a specific photolithographic mask, and a specific photolithographic procedure. The two interlaced patterns allow the creation of the capacitor node contact images, and the bit line contact holes images, to be formed in a thin polysilicon layer, with minimum spacing between contact images. Capacitor node contact holes, as well as bit line contact holes, are than formed in an insulator layer, via a dry etching procedure, using the patterned thin polysilicon layer as a mask. The use of specific masks, or of the interlaced pattern, allows the minimum spacing, between a capacitor node contact hole, and a bit line contact hole, to be limited only by the overlay between photolithographic masks.

Abstract: Contact holes are formed in a dielectric layer. An undoped polysilicon layer is formed on the dielectric layer and along the surface of the contact holes. A first photoresist is patterned on the dielectric layer to cover a region for forming P+ contact. Then, an ion implantation is carried out. A second photoresist is formed over the n conductivity type impurity regions in the cell area and the n+ conductive type impurity region in peripheral area. An ion implantation is then performed to dope ions into the substrate to form a p+ conductivity type impurity region in the peripheral area for PMOS. A titanium layer and a titanium nitride layer are respectively formed on the surface of the contact holes. Subsequently, a tungsten layer is refilled in to the contact holes. An etching back process or chemical mechanical polishing (CMP) is employed to removed a portion of the tungsten layer to form a plurality of tungsten plugs.

Abstract: A method was achieved for forming a multilayer passivation layer comprised of a silicon oxide/silicon nitride/silicon oxide/silicon nitride by depositing the layers consecutively in a single PECVD system. The method consists of depositing a first SiO.sub.2 layer that serves as a stress-release layer, a thin Si.sub.3 N.sub.4 layer that serves as a buffer layer that minimizes cracking and as a passivation layer that prevents mobile alkaline ion penetration, a thin second SiO.sub.2 layer to fill and seal any remaining cracks and pinholes in the first Si.sub.3 N.sub.4 layer, and a main Si.sub.3 N.sub.4 passivation layer that prevents water and/or other corrosive chemicals from attacking the metal. Since this multilayer passivation layer can be deposited essentially pinhole-free to a thickness that is less than the prior art's passivation layer of 8000 Angstroms needed to prevent pinholes, it can be used on 0.38 to 0.

Abstract: A method for simultaneous fabrication of an interlever metal contact and a fuse window reducing the number of masking steps required while providing a high yield for the fuse. A semiconductor substrate is provided having a device area with a first metal layer over an InterLevel Dielectric layer and a fuse area with a polysilicon fuse buried within the InterLevel Dielectric layer. A thick anti-reflective coating is formed on the first metal layer. The first metal layer and the anti-reflective coating are patterned to form a first metal line. An InterMetal Dielectric layer is formed over the InterLevel Dielectric layer and the first metal line. The InterMetal Dielectric layer, the InterLevel Dielectric layer, and the anti-reflective coating are patterned, simultaneously opening a via hole extending partially into the anti-reflective coating and a fuse window opening extending into the InterLevel Dielectric layer without exposing the fuse. An adhesion layer is formed over the InterMetal Dielectric layer.

Abstract: A process for fabricating a DRAM cell has been developed, in which two interlaced patterns, each comprised of capacitor node contact holes and bit line contact holes, are independently created, each using a specific photolithographic mask, and a specific photolithographic procedure. The two interlaced patterns allow the creation of the capacitor node contact images, and the bit line contact holes images, to be formed in a thin polysilicon layer, with minimum spacing between contact images. Capacitor node contact holes, as well as bit line contact holes, are than formed in an insulator layer, via a dry etching procedure, using the patterned thin polysilicon layer as a mask. The use of specific masks, or of the interlaced pattern, allows the minimum spacing, between a capacitor node contact hole, and a bit line contact hole, to be limited only by the overlay between photolithographic masks.

Abstract: This is a method of manufacture of a shallow trench isolation semiconductor device with STI trenches where an active area mask is provided for exposure of an active area during manufacture of the device comprises several following steps. The STI trenches are filled by coating the device with a blanket coating of silicon oxide. Coat the device with negative resist. Next, expose the negative resist layer with the active area mask for the device providing windows through the negative photoresist layer with an level of exposure energy provided to broaden the dimensions of exposure substantially laterally of the active area mask. Then, etch back the silicon oxide layer to a thin layer below the windows through the negative photoresist layer. Strip the resist. Finally, perform chemical mechanical planarization to remove excess silicon oxide from the surface.

Abstract: A crown capacitor for a memory device is formed using (1) an important early poly plug 42 process and (2) an etch barrier layer 34. A first insulating layer 30 and an etch barrier layer are formed over device structures and the substrate 10. A node contact hole 40 is formed through the etch barrier layer 34 and the first insulating layer 30. A plug 42 is formed filling the node contact hole 40. Next, a planarizing layer 44 is formed over the etch barrier layer 34 and the plug 42. A crown hole 46 is formed in the planarizing layer 44 exposing the plug 42. A first polysilicon layer 50 is deposited over the etch barrier layer, the plug 42, and the remaining first planarizing layer 44A. A Sacrificial layer 54 is formed over the first polysilicon layer 50 thereby filling the crown hole 46. The sacrificial layer 54 and the first polysilicon layer 50 are etch back to remove the exposed portions of the first polysilicon layer 50 over the planarizing layer 44A.

Abstract: A method of forming a capacitor having a cross section shape similar to the Greek letter psi. The shape of the capacitor plate provides a high capacitance using a modest amount of chip area. A capacitor hole is etched in a thick layer of a first dielectric. A layer of polysilicon is formed on the dielectric layer covering the sidewalls and bottom of the capacitor hole. A second dielectric is then used to fill the hole. A contact hole in the second dielectric extends to the contact region of the wafer and is filled with a polysilicon plug. The polysilicon plug and the polysilicon covering the sidewalls and bottom of the capacitor hole form the first capacitor plate. A layer of hemispherical grain polysilicon can be used to further increase the surface area of the first capacitor plate.

Abstract: In MOSFET devices with a pair of gate conductor stacks formed of a gate oxide layer, a gate electrode layer and a dielectric cap layer, LDD regions are formed by ion implanting lightly doped regions in the surface of the substrate. The LDD regions are self-aligned with the gate conductor stacks. Then form first dielectric spacers of a first dielectric material on the sidewalls of the gate conductor stacks; and form second dielectric spacers of a second dielectric material on the sidewalls of the first dielectric spacers adjacent to the gate conductor stacks thereby forming double sidewall spacers. Form fully doped regions ion implanted into the surface of the substrate self-aligned with the double sidewall spacers. The fully doped regions are self-aligned with the first and second dielectric spacers formed on the gate conductor stacks. The device is covered with a blanket dielectric layer formed by LPCVD from a TEOS source.

Abstract: A method for fabricating very narrow contacts on semiconductor substrate for increasing the packing density of devices on Ultra Large Scale Integration (ULSI) circuits was achieved. The method involves using conventional photolithographic techniques and anisotropic plasma etching to etch openings in a conducting layer and partially etch into an underlying planar insulating layer that covers and isolates the devices and device contact areas. Another conformal conducting layer is deposited on the substrate and in the openings and then etched back to form sidewall spacers in the openings. Using the original conducting layer and the sidewall spacers as an etch mask, the planar insulating layer is anisotropically etched within the sidewall spacers to form very narrow (small) contact opening to the desired device contact areas.

Abstract: A method was achieved for forming a multilayer passivation layer comprised of a silicon oxide/silicon nitride/silicon oxide/silicon nitride by depositing the layers consecutively in a single PECVD system. The method consists of depositing a first SiO.sub.2 layer that serves as a stress-release layer, a thin Si.sub.3 N.sub.4 layer that serves as a buffer layer that minimizes cracking and as a passivation layer that prevents mobile alkaline ion penetration, a thin second SiO.sub.2 layer to fill and seal any remaining cracks and pinholes in the first Si.sub.3 N.sub.4 layer, and a main Si.sub.3 N.sub.4 passivation layer that prevents water and/or other corrosive chemicals from attacking the metal. Since this multilayer passivation layer can be deposited essentially pinhole-free to a thickness that is less than the prior art's passivation layer of 8000 Angstroms needed to prevent pinholes, it can be used on 0.38 to 0.

Abstract: A polysilicon layer is deposited on a dielectric layer. A silicon oxynitride layer is then formed on the polysilicon layer. A photoresist is imprinted with a pattern on the silicon oxynitride layer to define the storage node. An etching step is used to etch the silicon oxynitride layer and the polysilicon layer to formed the storage node. A HSG silicon is deposited on the silicon oxynitride layer and on the side walls of the storage node. An isotropically etching step is performed to remove the HSG layer on the top of the storage node. The silicon oxynitride is then removed. A dielectric layer is then formed along the surface of the storage node. A conductive layer is deposited over the dielectric layer. The conductive layer is used as the top storage node.

Abstract: The preset invention provides a method of manufacturing miniature interconnects and capacitors for semiconductor memory devices. The method uses a configuration of two sets of spacers to form self aligned source/bit line contacts and capacitor storage electrodes. First spacers are formed on the sidewalls of an interlevel dielectric layer. The first spacers define the source/bit line contacts holes. Later, the second spacers are formed the sidewalls of the bit lines. The second spacers define the capacitor storage electrodes. The self-aligning process, which uses the two set of spacers, allows a wide processing overlay window for contact etching to form the contact holes and permits small contact holes with high aspect ratios. The method reduces the masking steps by defining both the source and drain contacts in the same masking step.

Abstract: In MOSFET devices with a pair of gate conductor stacks formed of a gate oxide layer, a gate electrode layer and a dielectric cap layer, LDD regions are formed by ion implanting lightly doped regions in the surface of the substrate. The LDD regions are self-aligned with the gate conductor stacks. Then form first dielectric spacers of a first dielectric material on the sidewalls of the gate conductor stacks; and form second dielectric spacers of a second dielectric material on the sidewalls of the first dielectric spacers adjacent to the gate conductor stacks thereby forming double sidewall spacers. Form fully doped regions ion implanted into the surface of the substrate self-aligned with the double sidewall spacers. The fully doped regions are self-aligned with the first and second dielectric spacers formed on the gate conductor stacks. The device is covered with a blanket dielectric layer formed by LPCVD from a TEOS source.

Abstract: A method of fabricating double and multi-cylindrical storage capacitors is provided. To form a double crown capacitor, a conductive layer is formed on a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole provided in the underlying insulation structure to thereby electrically connect the conductive layer with an active region of a transistor. A groove is formed in the conductive layer defining an area for a plurality of separated electrodes. First spacers are formed on the side walls of the groove. Then, the conductive layer is anisotrophically etched using the spacers as an etch mask thus forming an annular ridge around the area where the memory device is formed. The first spacers are then removed. Second and third spacers are then formed on the both sidewalls of the annular ridge.

Abstract: The present invention provides a method of manufacturing miniature interconnect for semiconductor devices. The method uses a configuration of spacers and etch barriers (silicon nitride cap layers) to form self aligned source and drain contacts. Antireflective silicon nitride cap layers and highly selective etches are used define smaller interconnect openings. First spacers are formed on the gate electrodes. Later, the second spacers are formed the sidewalls of a storage electrode hole formed in insulation layers over the gate electrodes. The inventive self-aligning process, which uses the two set of spacers, allows a wide processing window for contact etching to form the contact hole and permit a small contact hole aspect ratio. The method reduces the masking steps by defining both the source and drain contacts in the same masking step.

Abstract: A method is provided for fabricating a single crown electrode for a capacitor for semiconductor memory devices. A conductive layer is formed over a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole to thereby electrically connect the conductive layer with an active region of a transistor formed in the substrate Next, a novel groove is etched in the conductive layer between adjacent memory cells. Sidewall spacers are formed on the groove. The conductive layer is anisotropically etched using the spacers as an etching mask, thereby forming a plurality of electrodes having upright portions. The etching exposes the first insulation layer in the area under the grooves, but leaves a thickness of the base conductive layer to form the bottom of the electrode. The spacers then are removed and a conformal dielectric layer is formed over the surface. Lastly, a top plate electrode is formed over the conformal dielectric layer.

Abstract: An improved method for fabricating dynamic random access memory (DRAM) cell having a fin-shaped capacitor with increased capacitance was achieved. The capacitor is fabricated over the bit lines and makes contact to the source/drain area of a field effect transistor (FET). The capacitor with increased capacitance is formed by depositing an N doped polysilicon layer making electrical contact to the source/drain of the FET. A sacrificial oxide layer is deposited and a contact opening formed over the DRAM cell area to the polysilicon layer. A second polysilicon layer is deposited and patterned over the sacrificial oxide layer forming the top fin portion of the capacitor, which makes electrical contact to the first polysilicon layer through the contact opening. The sacrificial oxide layer is then completely removed by wet etching, while the underlying polysilicon layer provides a very important etch stop to protect the substrate structures.

Abstract: An improved process for fabricating an integrated circuit is achieved by forming a planar conductive layer over closely spaced structures, such as gate electrode structures of field effect transistors (FET) and the electrically interconnecting word line structures of DRAM and SRAM chips. The planar conductive layer is then patterned by plasma etching to form the next level of electrical interconnecting bit lines, which makes contact to the source/drain of the FETs. The process involves the conformal deposition of a relatively thick polysilicon layer to fill the submicrometer spaces in the underlying structure. An etch back of the polysilicon and the deposition of a metal silicide is used to form an essentially planar conducting layer. This locally planar layer over submicrometer spaced features, with high aspect ratios, provides an ideal surface for exposing and developing distortion free and residue free submicrometer photoresist images required for Ultra Large Semiconductor Integration (ULSI).