Patents by Inventor Inki Kim
Inki Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7241665Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.Type: GrantFiled: July 12, 2006Date of Patent: July 10, 2007Assignee: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ch'ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Charlie Tay, Chang Gi Lee, Hitomi Watanabe, Naoto Inoue
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Patent number: 7208378Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.Type: GrantFiled: May 10, 2005Date of Patent: April 24, 2007Assignee: SilterraInventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
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Publication number: 20060258116Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.Type: ApplicationFiled: July 12, 2006Publication date: November 16, 2006Applicant: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Kim, Min Paek, Ch'ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Ping, Wan Lee, Choong Chien, Charlie Tay, Chang Lee, Hitomi Watanabe, Naoto Inoue
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Patent number: 7091104Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.Type: GrantFiled: January 23, 2003Date of Patent: August 15, 2006Assignee: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ch'ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Gie Lee, Wan Gie Lee, Choong Shiau Chien, Charlie Tay, Chang Gi Lee, Hitomi Watanabe, Naoto Inoue
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Publication number: 20050287745Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.Type: ApplicationFiled: May 10, 2005Publication date: December 29, 2005Applicant: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Kim, Min Paek, Ong Teong, Oh Young, Ng Leng, Joung Ho
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Patent number: 6890822Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.Type: GrantFiled: February 13, 2003Date of Patent: May 10, 2005Assignee: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
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Publication number: 20050059215Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.Type: ApplicationFiled: October 25, 2004Publication date: March 17, 2005Applicant: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Kim, Min Paek, Chiew Ping, Wan Lee, Choong Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
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Patent number: 6818514Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.Type: GrantFiled: February 26, 2003Date of Patent: November 16, 2004Assignee: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
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Publication number: 20040166698Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.Type: ApplicationFiled: February 26, 2003Publication date: August 26, 2004Applicant: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
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Publication number: 20040161897Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.Type: ApplicationFiled: February 13, 2003Publication date: August 19, 2004Applicant: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
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Publication number: 20040147090Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.Type: ApplicationFiled: January 23, 2003Publication date: July 29, 2004Applicant: SilTerra Malaysia Sdn. Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ch?apos;ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Sin Pin, Wan Gie Lee, Choong Shiau Chien, Charlie Tay, Chang Gi Lee, Hitomi Watanabe, Naoto Inoue
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Patent number: 6290584Abstract: An improved workpiece carrier assembly includes a workpiece retaining assembly having a plurality of distinct retaining elements rather than a one-piece retaining ring. In accordance with one embodiment, a plurality of retaining segments reside within a like plurality of channels. The retaining segments may be individually or collectively controlled by a pressurized fluid system. In accordance with an alternate embodiment, a plurality of retaining pins reside within a like plurality of guide sleeves. The retaining pins may be individually or collectively controlled by a pressurized fluid system.Type: GrantFiled: August 13, 1999Date of Patent: September 18, 2001Assignee: SpeedFam-IPEC CorporationInventors: Inki Kim, Mark Meloni, Mike Park
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Patent number: 6113465Abstract: The present invention provides methods and apparatus for optimizing the removal of thin film layers during planarization of a semiconductor wafer to achieve global uniformity of the entire semiconductor surface while further achieving the planarity within an individual die structure. A wafer polishing system suitably comprises a wafer polishing apparatus, a controller and a wafer polishing recipe. The wafer polishing recipe may be comprised of various operational parameters utilized for controlling the operation of the polishing apparatus.Type: GrantFiled: June 16, 1998Date of Patent: September 5, 2000Assignees: SpeedFam-IPEC Corporation, Hewlett-Packard CompanyInventors: Inki Kim, Jim Xu
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Patent number: 6102779Abstract: In semiconductor wafer polishing, a backing pad is sized smaller than the wafer being polished so as to produce a desired backset, allowing the wafer to bend, thereby reducing over-polish at the wafer edge.Type: GrantFiled: November 5, 1998Date of Patent: August 15, 2000Assignee: Speedfam-IPEC, Inc.Inventors: Joseph V. Cesna, Inki Kim
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Patent number: 6089961Abstract: A ring extension is provided for use with a semiconductor wafer carrier. The ring extension has a radially inner surface, the lower portion of which contacts a peripheral edge of a wafer to confine the wafer during a polishing operation. A recess or groove is formed in the inner surface and a passageway extending through the ring extension provides pressure relief to prevent slurry build up.Type: GrantFiled: December 7, 1998Date of Patent: July 18, 2000Assignee: Speedfam-IPEC CorporationInventors: Joseph V. Cesna, Inki Kim
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Patent number: 5993293Abstract: In semiconductor wafer polishing, a backing pad is sized smaller than the wafer being polished so as to produce a desired backset, allowing the wafer to bend, thereby reducing over-polish at the wafer edge.Type: GrantFiled: June 17, 1998Date of Patent: November 30, 1999Assignee: Speedram CorporationInventors: Joseph V. Cesna, Inki Kim
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Patent number: 5989104Abstract: A carrier for semiconductor wafers to be polished comprises a rigid upper housing, a rigid pressure plate and a gimbal mechanism connecting the plate and housing which permits the plate to gimbal or wobble relative to the housing. The pressure plate is a one-piece component and has a central cut-out portion in which the gimbal mechanism is disposed, thereby establishing a low gimbal point and reducing the incidence of tilting. The gimbal mechanism has an inner bearing ring which is fastened to the underside of the housing, and an outer bearing ring which is fastened to an outer portion of the pressure plate.Type: GrantFiled: January 12, 1998Date of Patent: November 23, 1999Assignee: SpeedFam-IPEC CorporationInventors: Inki Kim, Chris Karlsrud, John Natalicio, James Schlueter, Thomas K. Crosby
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Patent number: 5921849Abstract: An apparatus for evenly polishing or planarizing the surfaces of workpieces includes a distributor with a reservoir and a plurality of conduits for uniformly guiding a fluid across a surface of a polishing material. The apparatus is configured to couple to a polishing machine that processes surfaces of workpieces such as semiconductor wafers and computer discs. The reservoir receives a fluid from an exterior source and the fluid is pooled in the reservoir before passing down the conduits to the polishing material. When multiple conduits are employed, the conduits are evenly spaced around the distributor to facilitate uniform application of fluid to a number of locations on the polishing material.Type: GrantFiled: June 4, 1997Date of Patent: July 13, 1999Assignee: Speedfam CorporationInventors: Inki Kim, Lawrence Vondra
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Patent number: 5695392Abstract: A retainer ring for retaining a thin workpiece during machining thereof, the retaining ring being of a design which facilitates distribution of an abrasive slurry used in the machining operation.Type: GrantFiled: April 19, 1996Date of Patent: December 9, 1997Assignee: Speedfam CorporationInventor: Inki Kim