Patents by Inventor Innocenzo Tortorelli
Innocenzo Tortorelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12125540Abstract: Methods, systems, and devices for improving write latency and energy using asymmetric cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.Type: GrantFiled: April 29, 2022Date of Patent: October 22, 2024Assignee: Micron Technology, Inc.Inventors: Mattia Robustelli, Innocenzo Tortorelli
-
Publication number: 20240347081Abstract: Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.Type: ApplicationFiled: April 11, 2024Publication date: October 17, 2024Inventors: Hernan A. Castro, Mattia Boniardi, Innocenzo Tortorelli
-
Publication number: 20240321347Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.Type: ApplicationFiled: April 23, 2024Publication date: September 26, 2024Inventors: Mattia Robustelli, Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano
-
Publication number: 20240312518Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.Type: ApplicationFiled: February 23, 2024Publication date: September 19, 2024Inventors: Innocenzo Tortorelli, Hari Giduturi, Fabio Pellizzer
-
Patent number: 12080365Abstract: Methods, systems, and devices for analog storing information are described herein. Such methods, systems and devices are suitable for synaptic weight storage in electronic neuro-biological mimicking architectures. A memory device may include a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality. Memory cells may be provided on different decks of a multi-deck memory array. A storage element material of a respective memory cell may have a thickness and/or a composition different from another thickness or composition of a respective storage element material of another respective memory cell on a different deck in the multi-deck memory array.Type: GrantFiled: January 28, 2020Date of Patent: September 3, 2024Assignee: Micron Technology, Inc.Inventors: Mattia Boniardi, Innocenzo Tortorelli
-
Patent number: 12075714Abstract: Methods, systems, and devices for random number generation based on threshold voltage randomness are described. For example, a memory device may apply a voltage to a chalcogenide element and increase the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element. The memory device may detect the state of an oscillating signal at a time at which the applied voltage satisfies the threshold voltage, and the memory device may output a logic value corresponding to the state of the oscillating signal. The threshold voltage of the chalcogenide element may vary in a statistically random manner across voltage applications, and hence the state of the oscillating signal at the time an applied voltage reaches the threshold voltage may likewise vary in a statistically random manner, and thus the corresponding logic value that is output may be a random value suitable for random number generation.Type: GrantFiled: August 9, 2022Date of Patent: August 27, 2024Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Matteo Impalà, Cécile Colette Solange Nail
-
Publication number: 20240233828Abstract: Methods, apparatuses and systems related to reading data from memory cells configured to store more than one bit are described. The apparatus may be configured to determine a polarity data associated with reading data stored at a target location. In reading the data stored at the target location, the apparatus may apply one or more voltage levels across different polarities according to the determined polarity data.Type: ApplicationFiled: October 20, 2022Publication date: July 11, 2024Inventors: Matteo Impala', Mattia Robustelli, Innocenzo Tortorelli
-
Patent number: 12033695Abstract: Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.Type: GrantFiled: May 9, 2022Date of Patent: July 9, 2024Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Alessandro Sebastiani, Mattia Robustelli, Matteo Impalà
-
Publication number: 20240221829Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.Type: ApplicationFiled: January 11, 2024Publication date: July 4, 2024Inventors: Innocenzo Tortorelli, Fabio Pellizzer, Mattia Robustelli, Alessandro Sebastiani
-
Publication number: 20240203468Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).Type: ApplicationFiled: March 1, 2024Publication date: June 20, 2024Inventors: Mattia Boniardi, Richard K. Dodge, Innocenzo Tortorelli, Mattia Robustelli, Mario Allegra
-
Patent number: 12014779Abstract: Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.Type: GrantFiled: August 10, 2022Date of Patent: June 18, 2024Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Mattia Boniardi, Mattia Robustelli
-
Publication number: 20240194258Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.Type: ApplicationFiled: February 23, 2024Publication date: June 13, 2024Inventors: Marco Sforzin, Paolo Amato, Innocenzo Tortorelli
-
Patent number: 11996141Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.Type: GrantFiled: April 8, 2022Date of Patent: May 28, 2024Assignee: Micron Technology, Inc.Inventors: Mattia Robustelli, Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano
-
Patent number: 11984191Abstract: Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.Type: GrantFiled: May 9, 2022Date of Patent: May 14, 2024Assignee: Micron Technology, Inc.Inventors: Hernan A. Castro, Mattia Boniardi, Innocenzo Tortorelli
-
Publication number: 20240135996Abstract: Methods, apparatuses and systems related to reading data from memory cells configured to store more than one bit are described. The apparatus may be configured to determine a polarity data associated with reading data stored at a target location. In reading the data stored at the target location, the apparatus may apply one or more voltage levels across different polarities according to the determined polarity data.Type: ApplicationFiled: October 19, 2022Publication date: April 25, 2024Inventors: Matteo Impala', Mattia Robustelli, Innocenzo Tortorelli
-
Publication number: 20240130143Abstract: A single memory chip including both memory and storage capabilities on the single chip and accompanying process for forming a memory array including both capabilities is disclosed. In particular, the single chip may incorporate the use of two different chalcogenide materials deposited thereon to implement the memory and storage capabilities. Chalcogenide materials provide flexibility on cell performance, such as by changing the chalcogenide material composition. For the single memory chip, one type of chalcogenide material may be utilized to create memory cells and another type of chalcogenide material may be utilized to create storage cells. The process for forming the memory array includes forming first and second openings in a starting structure and performing a series of etching and deposition steps on the structure to form the memory and storage cells using the two different chalcogenide compositions. The memory and storage cells are independently addressable via wordline and bitline selection.Type: ApplicationFiled: October 18, 2022Publication date: April 18, 2024Inventors: Innocenzo Tortorelli, Agostino Pirovano, Matteo Impalà, Mattia Robustelli, Fabio Pellizzer
-
Patent number: 11942183Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).Type: GrantFiled: October 15, 2021Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventors: Mattia Boniardi, Richard K. Dodge, Innocenzo Tortorelli, Mattia Robustelli, Mario Allegra
-
Patent number: 11923002Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.Type: GrantFiled: July 20, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Hari Giduturi, Fabio Pellizzer
-
Patent number: 11922056Abstract: An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.Type: GrantFiled: October 31, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Mattia Boniardi, Innocenzo Tortorelli
-
Patent number: 11915750Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.Type: GrantFiled: July 11, 2022Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Marco Sforzin, Paolo Amato, Innocenzo Tortorelli