Patents by Inventor Ionut Radu

Ionut Radu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8993461
    Abstract: A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 31, 2015
    Assignee: Soitec
    Inventors: Ionut Radu, Christophe Gourdel, Christelle Vetizou
  • Publication number: 20140357093
    Abstract: The invention relates to a process for stabilizing a bonding interface, located within a structure for applications in the fields of electronics, optics and/or optoelectronics and that comprises an oxide layer buried between an active layer and a receiver substrate, the bonding interface having been obtained by molecular adhesion. In accordance with the invention, the process further comprises irradiating this structure with a light energy flux provided by a laser, so that the flux, directed toward the structure, is absorbed by the energy conversion layer and converted to heat in this layer, and in that this heat diffuses into the structure toward the bonding interface, so as to thus stabilize the bonding interface.
    Type: Application
    Filed: December 13, 2012
    Publication date: December 4, 2014
    Inventors: Didier Landru, Carole David, Ionut Radu, Lucianna Capello, Yann Sinquin
  • Patent number: 8866305
    Abstract: Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: October 21, 2014
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8841742
    Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming recesses in the donor structure, implanting ions into the donor structure to form a generally planar, inhomogeneous weakened zone therein, and providing material within the recesses. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 23, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8759881
    Abstract: A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10?3 ohm·cm and a thermal conductivity of greater than 100 W·m?1·K?1, a bonding layer, a first seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, a second seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and an active layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and being present in a thickness of between 3 and 100 micrometers. The materials of the support substrate, the bonding layer and the first seed layer are refractory at a temperature of greater than 750° C., the active layer and second seed layer have a difference in lattice parameter of less than 0.005 ?, the active layer is crack-free, and the heterostructure has a specific contact resistance between the bonding layer and the first seed layer that is less than or equal to 0.1 ohm·cm2.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: June 24, 2014
    Assignee: Soitec
    Inventors: Jean-Marc Bethoux, Fabrice Letertre, Chris Werkhoven, Ionut Radu, Oleg Kononchuck
  • Patent number: 8716105
    Abstract: Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: May 6, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu, Didier Landru
  • Patent number: 8673733
    Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: March 18, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8623740
    Abstract: A method for producing a structure having an ultra thin buried oxide (UTBOX) layer by assembling a donor substrate with a receiver substrate wherein at least one of the substrates includes an insulating layer having a thickness of less than 50 nm that faces the other substrate, conducting a first heat treatment for reinforcing the assembly between the two substrates at temperature below 400° C., and conducting a second heat treatment at temperature above 900° C., wherein the exposure time between 400° C. and 900° C. between the heat treatments is less than 1 minute and advantageously less than 30 seconds.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: January 7, 2014
    Assignee: Soitec
    Inventors: Didier Landru, Ionut Radu, Sébastien Vincent
  • Publication number: 20130299997
    Abstract: Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.
    Type: Application
    Filed: July 9, 2013
    Publication date: November 14, 2013
    Inventors: Mariam Sadaka, Ionut Radu
  • Publication number: 20130256907
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Application
    Filed: May 22, 2013
    Publication date: October 3, 2013
    Inventors: Mariam Sadaka, Ionut Radu
  • Publication number: 20130217206
    Abstract: Methods of fabricating semiconductor devices include forming a metal silicide in a portion of a crystalline silicon layer, and etching the metal silicide using an etchant selective to the metal silicide relative to the crystalline silicon to provide a thin crystalline silicon layer. Silicon-on-insulator (SOI) substrates may be formed by providing a layer of crystalline silicon over a base substrate with a dielectric material between the layer of crystalline silicone and the base substrate, and thinning the layer of crystalline silicon by forming a metal silicide layer in a portion of the crystalline silicon, and then etching the metal silicide layer using an etchant selective to the metal silicide layer relative to the crystalline silicon.
    Type: Application
    Filed: February 22, 2012
    Publication date: August 22, 2013
    Applicant: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8501537
    Abstract: Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded metal structure. Annealing the first metal feature may comprise subjecting the first metal feature to a pre-bonding thermal budget, and annealing the bonded metal structure may comprise subjecting the bonded metal structure to a post-bonding thermal budget that is less than the pre-bonding thermal budget. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: August 6, 2013
    Assignees: Soitec, Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Mariam Sadaka, Ionut Radu, Didier Landru, Lea Di Cioccio
  • Patent number: 8481406
    Abstract: Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: July 9, 2013
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8461017
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: June 11, 2013
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Publication number: 20130075868
    Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Applicant: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu
  • Publication number: 20130032272
    Abstract: The present invention relates to an apparatus for the manufacture of semiconductor devices wherein the apparatus includes a bonding module that has a vacuum chamber to provide bonding of wafers under pressure below atmospheric pressure; and a loadlock module connected to the bonding module and configured for wafer transfer to the bonding module. The loadlock module is also connected to a first vacuum pumping device configured to reduce the pressure in the loadlock module to below atmospheric pressure. The bonding and loadlock modules remain at a pressure below atmospheric pressure while the wafer is transferred from the loadlock module into the bonding module.
    Type: Application
    Filed: September 21, 2012
    Publication date: February 7, 2013
    Applicant: SOITEC
    Inventors: Marcel Broekaart, Ionut Radu
  • Publication number: 20130026608
    Abstract: The invention relates to a process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate, comprising the following steps: (a) implanting ionic species in a source substrate comprising the said functionalized layer and a sacrificial buffer layer located under the functionalized layer relative to the direction of implantation, to a depth delimiting the thickness of an upper part of the source substrate comprising the functionalized layer and at least part of the buffer layer; (b) bonding the source substrate to the support substrate; (c) fracturing the source substrate and transferring the upper part of the source substrate to the support substrate; (d) removing the buffer layer by selective etching with respect to the functionalized layer.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 31, 2013
    Applicant: SOITEC
    Inventor: Ionut Radu
  • Publication number: 20130026663
    Abstract: A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 31, 2013
    Applicant: SOITEC
    Inventors: Ionut Radu, Christophe Gourdel, Christelle Vetizou
  • Publication number: 20120252162
    Abstract: Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded metal structure. Annealing the first metal feature may comprise subjecting the first metal feature to a pre-bonding thermal budget, and annealing the bonded metal structure may comprise subjecting the bonded metal structure to a post-bonding thermal budget that is less than the pre-bonding thermal budget. Bonded semiconductor structures are fabricated using such methods.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Applicants: COMMISSARIAT A L`ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Mariam Sadaka, Ionut Radu, Didier Landru, Lea Di Cioccio
  • Publication number: 20120252189
    Abstract: Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Mariam Sadaka, Ionut Radu, Didier Landru