Patents by Inventor Irina Vasilyeva
Irina Vasilyeva has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11050020Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: GrantFiled: May 8, 2020Date of Patent: June 29, 2021Assignee: Micron Technology, Inc.Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
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Publication number: 20210183697Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.Type: ApplicationFiled: March 1, 2021Publication date: June 17, 2021Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
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Patent number: 10879462Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: GrantFiled: May 8, 2020Date of Patent: December 29, 2020Assignee: Micron Technology, Inc.Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
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Publication number: 20200274059Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: ApplicationFiled: May 8, 2020Publication date: August 27, 2020Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
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Publication number: 20200274060Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: ApplicationFiled: May 8, 2020Publication date: August 27, 2020Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
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Patent number: 10665782Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: GrantFiled: August 23, 2018Date of Patent: May 26, 2020Assignee: Micron Technology, Inc.Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
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Patent number: 10658580Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: GrantFiled: December 29, 2017Date of Patent: May 19, 2020Assignee: Micron Technology, Inc.Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
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Patent number: 10249819Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: GrantFiled: April 3, 2014Date of Patent: April 2, 2019Assignee: Micron Technology, Inc.Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
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Publication number: 20180366645Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: ApplicationFiled: August 23, 2018Publication date: December 20, 2018Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
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Publication number: 20180123036Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
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Patent number: 9741612Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.Type: GrantFiled: February 23, 2016Date of Patent: August 22, 2017Assignee: Micron Technology, Inc.Inventors: Brandon P. Wirz, Keith Ypma, Christopher J. Gambee, Jaspreet S. Gandhi, Kevin M. Dowdle, Irina Vasilyeva, Yang Chao, Jon Hacker
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Publication number: 20160172242Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.Type: ApplicationFiled: February 23, 2016Publication date: June 16, 2016Inventors: Brandon P. Wirz, Keith Ypma, Christopher J. Gambee, Jaspreet S. Gandhi, Kevin M. Dowdle, Irina Vasilyeva, Yang Chao, Jon Hacker
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Patent number: 9299663Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.Type: GrantFiled: May 19, 2014Date of Patent: March 29, 2016Assignee: Micron Technology, Inc.Inventors: Brandon P. Wirz, Keith Ypma, Christopher J. Gambee, Jaspreet S. Gandhi, Kevin M. Dowdle, Irina Vasilyeva, Yang Chao, Jon Hacker
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Publication number: 20150333014Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.Type: ApplicationFiled: May 19, 2014Publication date: November 19, 2015Applicant: Micron Technology, Inc.Inventors: Brandon P. Wirz, Keith Ypma, Christopher J. Gambee, Jaspreet S. Gandhi, Kevin M. Dowdle, Irina Vasilyeva, Yang Chao, Jon Hacker
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Publication number: 20150287916Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: ApplicationFiled: April 3, 2014Publication date: October 8, 2015Applicant: Micron Technology, Inc.Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
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Publication number: 20150145146Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.Type: ApplicationFiled: February 3, 2015Publication date: May 28, 2015Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
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Patent number: 9034752Abstract: Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside surface of a substrate. A self-planarizing isolation material may be formed over the barrier material. An exposed surface of the self-planarizing isolation material may be substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of protruding material of the conductive vias may be removed to expose the conductive vias. Removal of the self-planarizing isolation material, the barrier material, and the conductive vias may be stopped after exposing at least one laterally extending portion of the barrier material.Type: GrantFiled: January 3, 2013Date of Patent: May 19, 2015Assignee: Micron Technology, Inc.Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
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Publication number: 20140183740Abstract: Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside surface of a substrate. A self-planarizing isolation material may be formed over the barrier material. An exposed surface of the self-planarizing isolation material may be substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of protruding material of the conductive vias may be removed to expose the conductive vias. Removal of the self-planarizing isolation material, the barrier material, and the conductive vias may be stopped after exposing at least one laterally extending portion of the barrier material.Type: ApplicationFiled: January 3, 2013Publication date: July 3, 2014Applicant: Micron Technology, Inc.Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
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Patent number: 8318578Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.Type: GrantFiled: October 7, 2009Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventors: Kevin Shea, Brett Busch, Farrell Good, Irina Vasilyeva, Vishwanath Bhat
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Publication number: 20100025362Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.Type: ApplicationFiled: October 7, 2009Publication date: February 4, 2010Applicant: Micron Technology, Inc.Inventors: Kevin Shea, Brett Busch, Farrell Good, Irina Vasilyeva, Vishwanath Bhat