Patents by Inventor Irina Vasilyeva

Irina Vasilyeva has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11050020
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Publication number: 20210183697
    Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.
    Type: Application
    Filed: March 1, 2021
    Publication date: June 17, 2021
    Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
  • Patent number: 10879462
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Publication number: 20200274059
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 27, 2020
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Publication number: 20200274060
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 27, 2020
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Patent number: 10665782
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Patent number: 10658580
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Patent number: 10249819
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: April 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Publication number: 20180366645
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Publication number: 20180123036
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 3, 2018
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Patent number: 9741612
    Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Keith Ypma, Christopher J. Gambee, Jaspreet S. Gandhi, Kevin M. Dowdle, Irina Vasilyeva, Yang Chao, Jon Hacker
  • Publication number: 20160172242
    Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.
    Type: Application
    Filed: February 23, 2016
    Publication date: June 16, 2016
    Inventors: Brandon P. Wirz, Keith Ypma, Christopher J. Gambee, Jaspreet S. Gandhi, Kevin M. Dowdle, Irina Vasilyeva, Yang Chao, Jon Hacker
  • Patent number: 9299663
    Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 29, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Keith Ypma, Christopher J. Gambee, Jaspreet S. Gandhi, Kevin M. Dowdle, Irina Vasilyeva, Yang Chao, Jon Hacker
  • Publication number: 20150333014
    Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.
    Type: Application
    Filed: May 19, 2014
    Publication date: November 19, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Keith Ypma, Christopher J. Gambee, Jaspreet S. Gandhi, Kevin M. Dowdle, Irina Vasilyeva, Yang Chao, Jon Hacker
  • Publication number: 20150287916
    Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 8, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
  • Publication number: 20150145146
    Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.
    Type: Application
    Filed: February 3, 2015
    Publication date: May 28, 2015
    Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
  • Patent number: 9034752
    Abstract: Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside surface of a substrate. A self-planarizing isolation material may be formed over the barrier material. An exposed surface of the self-planarizing isolation material may be substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of protruding material of the conductive vias may be removed to expose the conductive vias. Removal of the self-planarizing isolation material, the barrier material, and the conductive vias may be stopped after exposing at least one laterally extending portion of the barrier material.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: May 19, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
  • Publication number: 20140183740
    Abstract: Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside surface of a substrate. A self-planarizing isolation material may be formed over the barrier material. An exposed surface of the self-planarizing isolation material may be substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of protruding material of the conductive vias may be removed to expose the conductive vias. Removal of the self-planarizing isolation material, the barrier material, and the conductive vias may be stopped after exposing at least one laterally extending portion of the barrier material.
    Type: Application
    Filed: January 3, 2013
    Publication date: July 3, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
  • Patent number: 8318578
    Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: November 27, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Shea, Brett Busch, Farrell Good, Irina Vasilyeva, Vishwanath Bhat
  • Publication number: 20100025362
    Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.
    Type: Application
    Filed: October 7, 2009
    Publication date: February 4, 2010
    Applicant: Micron Technology, Inc.
    Inventors: Kevin Shea, Brett Busch, Farrell Good, Irina Vasilyeva, Vishwanath Bhat