Patents by Inventor Isamu Hasebe

Isamu Hasebe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4271466
    Abstract: A direct memory access control (DMAC) system, in a data processing system, includes at least a central processing unit and a memory, the memory being capable of storing and providing data in any one of several predetermined formats. A plurality of input/output control ports, each connecting a respective input/output device to a common data bus, control data transfer in either direction between the device and the memory. A direct memory access control unit is connected to the common data bus for receiving an access request signal from any of the plurality of input/output control ports, and is connected to the memory for providing thereto, in response to the access request signal, instructions at least as to the size and desired format of the data transfer. A bus switching unit connects the common data bus to the memory, and is connected to the direct memory access control unit for receiving the instructions.
    Type: Grant
    Filed: November 21, 1978
    Date of Patent: June 2, 1981
    Assignee: Panafacom Limited
    Inventors: Mitsuru Yamamoto, Jun Arai, Takao Isogawa, Isamu Hasebe
  • Patent number: 4128881
    Abstract: In a multiprocessor system having a plurality of processors, each of identical construction, each processor is internally equipped with a fixed address supply source which generates a non-unique fixed address for accessing a common memory unit over commonly connected bus lines, and a sequential state indicate signal generator for generating a logic "1" or "0" synchronizing signal when a special condition (for example, interrupt) occurs with respect to the processor.A shared memory access control system for a multiprocessor system, as above described, includes circuitry, external to and associated with at least each processor except for one processor, responsive to the synchronizing signal from its respective processor for modifying the non-unique fixed address from the respective processor so that, as a result, each processor is able to address the common memory over the commonly connected bus lines with a unique fixed address.
    Type: Grant
    Filed: February 18, 1976
    Date of Patent: December 5, 1978
    Assignee: Panafacom Limited
    Inventors: Mitsuru Yamamoto, Jun Arai, Takao Isogawa, Isamu Hasebe