Patents by Inventor Isao Obu
Isao Obu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190115457Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.Type: ApplicationFiled: October 4, 2018Publication date: April 18, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Shigeki KOYA, Isao OBU
-
Patent number: 10249620Abstract: A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.Type: GrantFiled: May 10, 2018Date of Patent: April 2, 2019Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Shigeru Yoshida, Kaoru Ideno
-
Publication number: 20190088768Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.Type: ApplicationFiled: September 7, 2018Publication date: March 21, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
-
Publication number: 20190051645Abstract: A semiconductor device includes a sub-collector layer disposed on a substrate, a bipolar transistor including a collector layer formed of a semiconductor having a lower carrier concentration than the sub-collector layer, a base layer, and an emitter layer, and a protection diode including a Schottky electrode. The Schottky electrode forms, in a partial region of an upper surface of the collector layer, a Schottky junction to the collector layer and is connected to one of the base layer and the emitter layer. In the collector layer, a part that forms a junction to the base layer and a part that forms a junction to the Schottky electrode are electrically connected to each other via the collector layer.Type: ApplicationFiled: July 17, 2018Publication date: February 14, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Kenji SASAKI, Isao OBU
-
Patent number: 10192862Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.Type: GrantFiled: February 22, 2018Date of Patent: January 29, 2019Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Takayuki Tsutsui, Isao Obu, Yasuhisa Yamamoto
-
Patent number: 10163829Abstract: A compound semiconductor substrate has a first main surface parallel to a first direction and a second direction perpendicular to the first direction, a second main surface located on a side opposite to the first main surface, and a recess. The recess has an opening, a bottom surface facing the opening, and a plurality of side surfaces located between the opening and the bottom surface. The side surfaces include at least one first side surface forming an angle of about ? degrees with the bottom surface in the recess and at least one second side surface forming an angle of about ? degrees with the bottom surface in the recess. The total length of edge lines between the first main surface and the at least one first side surface is larger than that of edge lines between the first main surface and the at least one second side surface.Type: GrantFiled: December 6, 2017Date of Patent: December 25, 2018Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata
-
Patent number: 10134842Abstract: A high-performance HBT that is unlikely to decrease the process controllability and to increase the manufacturing cost is implemented. A heterojunction bipolar transistor includes an emitter layer, a base layer, and a collector layer on a GaAs substrate. The emitter layer is formed of InGaP. The base layer is formed of GaAsPBi having a composition that substantially lattice-matches GaAs.Type: GrantFiled: May 8, 2017Date of Patent: November 20, 2018Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Shigeru Yoshida
-
Publication number: 20180331208Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.Type: ApplicationFiled: July 3, 2018Publication date: November 15, 2018Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Shigeki KOYA, Isao OBU
-
Publication number: 20180309417Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.Type: ApplicationFiled: April 5, 2018Publication date: October 25, 2018Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Kenichi NAGURA
-
Publication number: 20180269206Abstract: A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.Type: ApplicationFiled: May 10, 2018Publication date: September 20, 2018Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Shigeru YOSHIDA, Kaoru IDENO
-
Publication number: 20180247926Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.Type: ApplicationFiled: February 22, 2018Publication date: August 30, 2018Applicant: Murata Manufacturing Co., Ltd.Inventors: Kenji SASAKI, Takayuki TSUTSUI, Isao OBU, Yasuhisa YAMAMOTO
-
Publication number: 20180240766Abstract: A compound semiconductor substrate has a first main surface parallel to a first direction and a second direction perpendicular to the first direction, a second main surface located on a side opposite to the first main surface, and a recess. The recess has an opening, a bottom surface facing the opening, and a plurality of side surfaces located between the opening and the bottom surface. The side surfaces include at least one first side surface forming an angle of about ? degrees with the bottom surface in the recess and at least one second side surface forming an angle of about ? degrees with the bottom surface in the recess. The total length of edge lines between the first main surface and the at least one first side surface is larger than that of edge lines between the first main surface and the at least one second side surface.Type: ApplicationFiled: December 6, 2017Publication date: August 23, 2018Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Yasunari Umemoto, Masahiro Shibata
-
Publication number: 20180240725Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.Type: ApplicationFiled: February 19, 2018Publication date: August 23, 2018Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata
-
Publication number: 20180240899Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.Type: ApplicationFiled: February 17, 2018Publication date: August 23, 2018Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari Umemoto, Shigeki Koya, Isao Obu
-
Patent number: 10056476Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.Type: GrantFiled: February 17, 2018Date of Patent: August 21, 2018Assignee: Murata Manufacturing Co., Ltd.Inventors: Yasunari Umemoto, Shigeki Koya, Isao Obu
-
Patent number: 9997516Abstract: A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.Type: GrantFiled: March 1, 2017Date of Patent: June 12, 2018Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Shigeru Yoshida, Kaoru Ideno
-
Publication number: 20180097092Abstract: An HBT includes a semiconductor substrate having first and second principal surfaces opposite each other; and a collector layer, a base layer, and an emitter layer stacked in this order on the first principal surface side of the semiconductor substrate. The collector layer includes a first semiconductor layer with metal particles dispersed therein, the metal particles each formed by a plurality of metal atoms bonded with each other.Type: ApplicationFiled: November 22, 2017Publication date: April 5, 2018Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Yasunari UMEMOTO, Shigeru YOSHIDA, Masahiro SHIBATA
-
Publication number: 20180012979Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, an emitter layer, and a semiconductor layer that are laminated in this order, wherein the emitter layer includes a first region having an upper surface on which the semiconductor layer is laminated, and a second region being adjacent to the first region and having an upper surface that is exposed, and the first and second regions of the emitter layer have higher doping concentrations in portions near the upper surfaces than in portions near an interface between the emitter layer and the base layer.Type: ApplicationFiled: May 18, 2017Publication date: January 11, 2018Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Yasunari UMEMOTO, Shigeki KOYA, Shigeru YOSHIDA, Isao OBU
-
Patent number: 9859405Abstract: An HBT includes a semiconductor substrate having first and second principal surfaces opposite each other; and a collector layer, a base layer, and an emitter layer stacked in this order on the first principal surface side of the semiconductor substrate. The collector layer includes a first semiconductor layer with metal particles dispersed therein, the metal particles each formed by a plurality of metal atoms bonded with each other.Type: GrantFiled: June 1, 2017Date of Patent: January 2, 2018Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Shigeru Yoshida, Masahiro Shibata
-
Publication number: 20170359030Abstract: A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.Type: ApplicationFiled: March 1, 2017Publication date: December 14, 2017Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Isao OBU, Shigeru YOSHIDA, Kaoru IDENO