Patents by Inventor Isao Yoshida

Isao Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4351674
    Abstract: A region containing a high concentration of impurity and a desired region adjacent thereto are fused by irradiation with a laser beam, to diffuse the impurity in the lateral direction into the desired region and to render the desired region a low resistance.Since this method can execute only the lateral diffusion of the impurity without affecting other portions, it is very useful for forming a high breakdown voltage MIS-FET, a resistor etc.
    Type: Grant
    Filed: August 29, 1980
    Date of Patent: September 28, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Isao Yoshida, Yasuo Wada, Masao Tamura, Masanobu Miyao, Makoto Ohkura, Nobuyoshi Natsuaki, Takashi Tokuyama
  • Patent number: 4317055
    Abstract: A high-voltage circuit for insulated gate field-effect transistors (MOSFETs) is provided wherein two MOSFETs are connected in series, the source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the high-voltage circuit, the drain of the second MOSFET being used as a drain terminal of the circuit. First and second resistors are connected in series between the source terminal and the drain terminal, and a biasing voltage supply is connected between the juncture of both the resistors and the gate of the second MOSFET. By virtue of these connections the "on" resistance of the high-voltage circuit is improved due to the effect of the biasing voltage effect in bringing the second MOSFET into an "on" condition.
    Type: Grant
    Filed: May 8, 1979
    Date of Patent: February 23, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Isao Yoshida, Minoru Nagata, Shikayuki Ochi, Hisao Katto
  • Patent number: 4296216
    Abstract: A thermoplastic resin composition excellent in coating property which comprises (A) at least one of polyamide resins and polyacetal resins, (B) at least one of aromatic monovinyl compound/vinyl cyanide copolymers comprising units of aromatic monovinyl compounds and units of vinyl cyanides in a weight ratio of 60:40 to 80:20 and having an intrinsic viscosity of 0.3 to 1.1 and (C) at least one of conjugated diene rubber/vinyl cyanide graft copolymers comprising units of conjugated diene rubbers in an amount of 5 to 45% by weight based on the weight of the graft copolymers in a weight proportion of the components (A), (B) and (C) being 0.1-10: 5-90: 5-94.9.
    Type: Grant
    Filed: March 5, 1980
    Date of Patent: October 20, 1981
    Assignee: Sumitomo Naugatuck Co., Ltd.
    Inventors: Hajime Sakano, Mikio Kodama, Koichi Nakayama, Isao Yoshida, Atsunori Inoue
  • Patent number: 4234835
    Abstract: Speed control apparatus for DC motor comprising a current mirror circuit including a first transistor 11 and second transistors 12-14 with their bases connected in common, the collectors of the second transistors 12-14 being in-common connected to one end of the DC motor 9 so as to control the motor current, the bases of the transistors being fed with such base current that saturates the transistors, thereby to raise their maximum controlling torque and starting torque of the DC motor.
    Type: Grant
    Filed: November 3, 1978
    Date of Patent: November 18, 1980
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuharu Ota, Isao Yoshida, Hiromitsu Nakano
  • Patent number: 4228051
    Abstract: A thermoplastic resin composition having a good heat cycle property which comprises (A) a graft polymer comprising a conjugated diene rubber and an aromatic vinyl compound and a vinylic cyanide grafted thereon in a weight proportion of 5-80:15-140, the weight ratio of the aromatic vinyl compound and the vinylic cyanide being 10-90:5-50, (B) a copolymer comprising an aromatic vinyl compound and a vinylic cyanide in a weight ratio of 40:60 to 90:10 and (C) an organo-silicon compound, the weight proportion of the graft polymer (A) and the copolymer (B) being from 5:95 to 95:5 and the amount of the organo-silicon compound (C) being from 0.05 to 3.0 parts by weight to 100 parts by weight of the combined amount of graft polymer (A) and the copolymer (B).
    Type: Grant
    Filed: July 31, 1979
    Date of Patent: October 14, 1980
    Assignee: Sumitomo Naugatuck Co., Ltd.
    Inventors: Hajime Sakano, Mikio Kodama, Toshihiro Shoji, Isao Yoshida
  • Patent number: 4213140
    Abstract: An insulated-gate semiconductor device wherein a first region is formed in the surface of a semiconductor substrate, the first region having a conductivity type opposite to that of the substrate, two insulated-gate FET's are formed within the first region, the drain of the first insulated-gate FET and that of the second insulated-gate FET are made common, the drains are electrically connected to the first region, and the gate of the first insulated-gate FET and the source of the second insulated-gate FET, and the gate of the second insulated-gate FET and the source of the first insulated-gate FET are respectively connected, thereby to prevent the occurrence of a negative resistance.
    Type: Grant
    Filed: July 6, 1978
    Date of Patent: July 15, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Takeaki Okabe, Isao Yoshida, Mineo Katsueda, Hidefumi Ito, Masatomo Furumi, Shikayuki Ochi
  • Patent number: 4189666
    Abstract: A speed control system for a d-c electric motor comprising a three-terminal space control IC to provide a constant voltage source having a negative internal resistance equal in absolute value to the internal resistance of the motor and thereby render the motor rotatable at a constant controlled speed. A resistance element having a positive temperature coefficient is used as an external circuit element for the IC so that rotation speed variations relative to load torque variations will be substantially constant despite variations in the ambient temperature.
    Type: Grant
    Filed: May 11, 1978
    Date of Patent: February 19, 1980
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshio Tetsugu, Hiromitsu Nakano, Hiroshi Minakuchi, Tomio Oyama, Isao Yoshida, Mitsuharu Ota, Kazutsugu Kobayashi
  • Patent number: 4179341
    Abstract: A method for preparation of a plated product which comprises electroplating a molded product of a resin composition comprising at least one kind of thermoplastic resin and carbon black having an oil absorption amount of not less than 200 ml/100 g and a surface area of not less than 500 m.sup.2 /g in a weight proportion of 100:3-100 and having an intrinsic volume resistivity of not more than 10.sup.3 .OMEGA..cm without previous electroless plating.
    Type: Grant
    Filed: June 12, 1978
    Date of Patent: December 18, 1979
    Assignee: Sumitomo Naugatuck Co., Ltd.
    Inventors: Hajime Sakano, Shigemitsu Kawagishi, Mikio Kodama, Akitoshi Ito, Toshihiro Shoji, Miyuki Terada, Isao Yoshida
  • Patent number: 4172260
    Abstract: In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, said high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode
    Type: Grant
    Filed: November 21, 1977
    Date of Patent: October 23, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Takeaki Okabe, Isao Yoshida, Shikayuki Ochi, Hidefumi Itoh, Masatomo Furumi, Toru Toyabe, Mineo Katsueda, Yukio Shirota
  • Patent number: 4086642
    Abstract: A protective circuit comprises a metal-oxide-semiconductor field effect transistor (MOSFET) to be protected, and a depletion-type MOSFET the gate and source of which are connected to each other and the souce of which is connected to the gate of the MOSFET to be protected, whereby the protective circuit which is suitable for a high-speed operation is completed.
    Type: Grant
    Filed: January 13, 1976
    Date of Patent: April 25, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Isao Yoshida, Ryoichi Hori, Hiroo Masuda, Osamu Minato, Jun Etoh, Masaaki Nakai
  • Patent number: 4005450
    Abstract: An insulated gate field effect transistor formed on one main surface of a semiconductor substrate comprises a drain region the impurity concentration of which is lower than twice that of the semiconductor substrate and the conductivity type is reverse to that of the substrate and a region of a high impurity concentration, formed in the low impurity concentration region, the conductivity type of which is the same as that of the low impurity concentration region.
    Type: Grant
    Filed: December 16, 1974
    Date of Patent: January 25, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Isao Yoshida, Takeshi Tokuyama, Shigeru Nishimatsu, Takahide Ikeda