Patents by Inventor Israel Diamand
Israel Diamand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11422939Abstract: Disclosed embodiments relate to a shared read request (SRR) using a common request tracker (CRT) as a temporary cache. In one example, a multi-core system includes a memory and a memory controller to receive a SRR from a core when a Leader core is not yet identified, allocate a CRT entry and store the SRR therein, mark it as a Leader, send a read request to a memory address indicated by the SRR, and when read data returns from the memory, store the read data in the CRT entry, send the read data to the Leader core, and await receipt, unless already received, of another SRR from a Follower core, the other SRR having a same address as the SRR, then, send the read data to the Follower core, and deallocate the CRT entry.Type: GrantFiled: December 26, 2019Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Israel Diamand, Ravi K. Venkatesan, Shlomi Shua, Oz Shitrit, Michael Behar, Roni Rosner
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Patent number: 11188467Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.Type: GrantFiled: September 28, 2017Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Israel Diamand, Alaa R. Alameldeen, Sreenivas Subramoney, Supratik Majumder, Srinivas Santosh Kumar Madugula, Jayesh Gaur, Zvika Greenfield, Anant V. Nori
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Publication number: 20210342134Abstract: Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.Type: ApplicationFiled: September 26, 2020Publication date: November 4, 2021Applicant: Intel CorporationInventors: Ahmad Yasin, Lihu Rappoport, Jared W. Stark, Jeffrey Baxter, Israel Diamand, Pavel Fridman, Ibrahim Hur, Nir Tell
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Patent number: 11151074Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.Type: GrantFiled: August 15, 2019Date of Patent: October 19, 2021Assignee: Intel CorporationInventors: Israel Diamand, Roni Rosner, Ravi Venkatesan, Shlomi Shua, Oz Shitrit, Henrietta Bezbroz, Alexander Gendler, Ohad Falik, Zigi Walter, Michael Behar, Shlomi Alkalay
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Publication number: 20210200675Abstract: Disclosed embodiments relate to a shared read request (SRR) using a common request tracker (CRT) as a temporary cache. In one example, a multi-core system includes a memory and a memory controller to receive a SRR from a core when a Leader core is not yet identified, allocate a CRT entry and store the SRR therein, mark it as a Leader, send a read request to a memory address indicated by the SRR, and when read data returns from the memory, store the read data in the CRT entry, send the read data to the Leader core, and await receipt, unless already received, of another SRR from a Follower core, the other SRR having a same address as the SRR, then, send the read data to the Follower core, and deallocate the CRT entry.Type: ApplicationFiled: December 26, 2019Publication date: July 1, 2021Applicant: Intel CorporationInventors: Israel DIAMAND, Ravi K. VENKATESAN, Shlomi SHUA, Oz SHITRIT, Michael BEHAR, Roni ROSNER
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Patent number: 11042315Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.Type: GrantFiled: March 29, 2018Date of Patent: June 22, 2021Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Christopher E. Cox, Navneet Dour, Asaf Rubinstein, Israel Diamand
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Patent number: 11036277Abstract: Methods and apparatus to dynamically throttle compute engines are disclosed. A disclosed example apparatus includes one or more compute engines to perform calculations, where the one or more compute engines are to cause a total power request to be issued based on the calculations. The example apparatus also includes a power management unit to receive the total power request and respond to the total power request. The apparatus also includes a throttle manager to adjust a throttle speed of at least one of the one or more compute engines based on comparing a minimum of the power request and a granted power to a total used power of the one or more compute engines prior to the power management unit responding to the total power request.Type: GrantFiled: August 15, 2019Date of Patent: June 15, 2021Assignee: Intel CorporationInventors: Israel Diamand, Avital Paz, Eran Nevet, Zigi Walter
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Publication number: 20210056030Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.Type: ApplicationFiled: November 6, 2020Publication date: February 25, 2021Inventors: Israel DIAMAND, Alaa R. ALAMELDEEN, Sreenivas SUBRAMONEY, Supratik MAJUMDER, Srinivas Santosh Kumar MADUGULA, Jayesh GAUR, Zvika GREENFIELD, Anant V. NORI
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Patent number: 10915453Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.Type: GrantFiled: December 29, 2016Date of Patent: February 9, 2021Assignee: Intel CorporationInventors: Israel Diamand, Zvika Greenfield, Julius Mandelblat, Asaf Rubinstein
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Patent number: 10761594Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.Type: GrantFiled: June 15, 2017Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Israel Diamand, Asaf Rubinstein, Arik Gihon, Tal Kuzi, Tomer Ziv, Nadav Shulman
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Patent number: 10558602Abstract: A transmitter comprising an input data buffer to store a plurality of bytes received on a first interconnect; multiplexer circuitry coupled to the input data buffer; and an output buffer coupled to the multiplexer circuitry, a second interconnect, and a third interconnect. The multiplexer circuitry is to: receive byte enable information in the input data buffer; determine that one or more of the plurality of bytes stored in the input data buffer are invalid; store an indicator in the output buffer; store valid bytes of the plurality of bytes in the output buffer to transmit on the third interconnect; and store the byte enable information in the output buffer to transmit on the third interconnect.Type: GrantFiled: September 13, 2018Date of Patent: February 11, 2020Assignee: Intel CorporationInventor: Israel Diamand
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Publication number: 20190369694Abstract: Methods and apparatus to dynamically throttle compute engines are disclosed. A disclosed example apparatus includes one or more compute engines to perform calculations, where the one or more compute engines are to cause a total power request to be issued based on the calculations. The example apparatus also includes a power management unit to receive the total power request and respond to the total power request. The apparatus also includes a throttle manager to adjust a throttle speed of at least one of the one or more compute engines based on comparing a minimum of the power request and a granted power to a total used power of the one or more compute engines prior to the power management unit responding to the total power request.Type: ApplicationFiled: August 15, 2019Publication date: December 5, 2019Inventors: Israel Diamand, Avital Paz, Eran Nevet, Zigi Walter
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Publication number: 20190370209Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.Type: ApplicationFiled: August 15, 2019Publication date: December 5, 2019Inventors: Israel Diamand, Roni Rosner, Ravi Venkatesan, Shlomi Shua, Oz Shitrit, Henrietta Bezbroz, Alexander Gendler, Ohad Falik, Zigi Walter, Michael Behar, Shlomi Alkalay
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Patent number: 10304418Abstract: An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.Type: GrantFiled: September 27, 2016Date of Patent: May 28, 2019Assignee: Intel CorporationInventors: Daniel Greenspan, Randy Osborne, Zvika Greenfield, Israel Diamand, Asaf Rubinstein
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Publication number: 20190095331Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Israel DIAMAND, Alaa R. ALAMELDEEN, Sreenivas SUBRAMONEY, Supratik MAJUMDER, Srinivas Santosh Kumar MADUGULA, Jayesh GAUR, Zvika GREENFIELD, Anant V. NORI
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Patent number: 10241916Abstract: Provided are an apparatus, system, and method for sparse superline removal. In response to occupancy of a replacement tracker (RT) exceeding an RT eviction watermark, an eviction process is triggered for evicting a superline from a sectored cache storing at least one superline. An eviction candidate is selected from superlines that have: 1) a sector usage below or equal to a superline low watermark and 2) an RT timestamp that is greater than a superline age watermark.Type: GrantFiled: March 31, 2017Date of Patent: March 26, 2019Assignee: INTEL CORPORATIONInventors: Zvika Greenfield, Zeshan A. Chishti, Israel Diamand
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Patent number: 10204047Abstract: An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.Type: GrantFiled: March 27, 2015Date of Patent: February 12, 2019Assignee: Intel CorporationInventors: Israel Diamand, Nir Misgav, Aravindh Anantaraman, Zvika Greenfield
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Publication number: 20190042131Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.Type: ApplicationFiled: March 29, 2018Publication date: February 7, 2019Inventors: Lakshminarayana PAPPU, Christopher E. COX, Navneet DOUR, Asaf RUBINSTEIN, Israel DIAMAND
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Patent number: 10176099Abstract: An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.Type: GrantFiled: July 11, 2016Date of Patent: January 8, 2019Assignee: Intel CorporationInventors: Jayesh Gaur, Supratik Majumder, Zvika Greenfield, Israel Diamand
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Publication number: 20180285271Abstract: Provided are an apparatus, system, and method for sparse superline removal. In response to occupancy of a replacement tracker (RT) exceeding an RT eviction watermark, an eviction process is triggered for evicting a superline from a sectored cache storing at least one superline. An eviction candidate is selected from superlines that have: 1) a sector usage below or equal to a superline low watermark and 2) an RT timestamp that is greater than a superline age watermark.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Zvika GREENFIELD, Zeshan A. CHISHTI, Israel DIAMAND