Patents by Inventor Israel Diamand

Israel Diamand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10761594
    Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Israel Diamand, Asaf Rubinstein, Arik Gihon, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • Patent number: 10558602
    Abstract: A transmitter comprising an input data buffer to store a plurality of bytes received on a first interconnect; multiplexer circuitry coupled to the input data buffer; and an output buffer coupled to the multiplexer circuitry, a second interconnect, and a third interconnect. The multiplexer circuitry is to: receive byte enable information in the input data buffer; determine that one or more of the plurality of bytes stored in the input data buffer are invalid; store an indicator in the output buffer; store valid bytes of the plurality of bytes in the output buffer to transmit on the third interconnect; and store the byte enable information in the output buffer to transmit on the third interconnect.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventor: Israel Diamand
  • Publication number: 20190369694
    Abstract: Methods and apparatus to dynamically throttle compute engines are disclosed. A disclosed example apparatus includes one or more compute engines to perform calculations, where the one or more compute engines are to cause a total power request to be issued based on the calculations. The example apparatus also includes a power management unit to receive the total power request and respond to the total power request. The apparatus also includes a throttle manager to adjust a throttle speed of at least one of the one or more compute engines based on comparing a minimum of the power request and a granted power to a total used power of the one or more compute engines prior to the power management unit responding to the total power request.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Israel Diamand, Avital Paz, Eran Nevet, Zigi Walter
  • Publication number: 20190370209
    Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Israel Diamand, Roni Rosner, Ravi Venkatesan, Shlomi Shua, Oz Shitrit, Henrietta Bezbroz, Alexander Gendler, Ohad Falik, Zigi Walter, Michael Behar, Shlomi Alkalay
  • Patent number: 10304418
    Abstract: An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Daniel Greenspan, Randy Osborne, Zvika Greenfield, Israel Diamand, Asaf Rubinstein
  • Publication number: 20190095331
    Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Israel DIAMAND, Alaa R. ALAMELDEEN, Sreenivas SUBRAMONEY, Supratik MAJUMDER, Srinivas Santosh Kumar MADUGULA, Jayesh GAUR, Zvika GREENFIELD, Anant V. NORI
  • Patent number: 10241916
    Abstract: Provided are an apparatus, system, and method for sparse superline removal. In response to occupancy of a replacement tracker (RT) exceeding an RT eviction watermark, an eviction process is triggered for evicting a superline from a sectored cache storing at least one superline. An eviction candidate is selected from superlines that have: 1) a sector usage below or equal to a superline low watermark and 2) an RT timestamp that is greater than a superline age watermark.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Zvika Greenfield, Zeshan A. Chishti, Israel Diamand
  • Patent number: 10204047
    Abstract: An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Israel Diamand, Nir Misgav, Aravindh Anantaraman, Zvika Greenfield
  • Publication number: 20190042131
    Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.
    Type: Application
    Filed: March 29, 2018
    Publication date: February 7, 2019
    Inventors: Lakshminarayana PAPPU, Christopher E. COX, Navneet DOUR, Asaf RUBINSTEIN, Israel DIAMAND
  • Patent number: 10176099
    Abstract: An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Jayesh Gaur, Supratik Majumder, Zvika Greenfield, Israel Diamand
  • Publication number: 20180285271
    Abstract: Provided are an apparatus, system, and method for sparse superline removal. In response to occupancy of a replacement tracker (RT) exceeding an RT eviction watermark, an eviction process is triggered for evicting a superline from a sectored cache storing at least one superline. An eviction candidate is selected from superlines that have: 1) a sector usage below or equal to a superline low watermark and 2) an RT timestamp that is greater than a superline age watermark.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Zvika GREENFIELD, Zeshan A. CHISHTI, Israel DIAMAND
  • Publication number: 20180189192
    Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Israel DIAMAND, Zvika GREENFIELD, Julius MANDELBLAT, Asaf RUBINSTEIN
  • Publication number: 20180089096
    Abstract: An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.
    Type: Application
    Filed: September 27, 2016
    Publication date: March 29, 2018
    Applicant: Intel Corporation
    Inventors: Daniel Greenspan, Randy Osborne, Zvika Greenfield, Israel Diamand, Asaf Rubinstein
  • Publication number: 20180011790
    Abstract: An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.
    Type: Application
    Filed: July 11, 2016
    Publication date: January 11, 2018
    Inventors: Jayesh Gaur, Supratik Majumder, Zvika Greenfield, Israel Diamand
  • Publication number: 20170285703
    Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.
    Type: Application
    Filed: June 15, 2017
    Publication date: October 5, 2017
    Inventors: Israel Diamand, Asaf Rubinstein, Arik Gihon, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • Patent number: 9767041
    Abstract: Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in the cache memory, perform a lookup operation for the first data element in the volatile memory and in response to a failed lookup operation, to generate a cache scrub hint forward the cache scrub hint to a cache scrub engine and identify one or more cache lines to scrub based at least in part on the cache scrub hint. Other examples are also disclosed and claimed.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Aravindh V. Anantaraman, Zvika Greenfield, Israel Diamand, Anant V. Nori, Pradeep Ramachandran, Nir Misgav
  • Patent number: 9710054
    Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2015
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Israel Diamand, Asaf Rubinstein, Arik Gihon, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • Publication number: 20170091099
    Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level system memory. The multi-level system memory has a near memory level and a far memory level. The near memory level has a sectored cache to cache super lines having multiple cache lines as a single cacheable item. The memory controller has tracker circuitry to track status information of an old request super line and a new request super-line that compete for a same slot within the sectored cache, wherein, the status information includes an identification of which one of the old and new super-lines is currently cached in the sectored cache.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: ZVIKA GREENFIELD, ISRAEL DIAMAND
  • Patent number: 9582430
    Abstract: Embodiments are generally directed to an asymmetric set combined cache including a direct-mapped cache portion and a multi-way cache portion. A processor may include one or more processing cores for processing of data, and a cache memory to cache data from a main memory for the one or more processing cores, the cache memory including a first cache portion, the first cache portion including a direct-mapped cache, and a second cache portion, the second cache portion including a multi-way cache. The cache memory includes asymmetric sets in the first cache portion and the second cache portion, the first cache portion being larger than the second cache portion. A coordinated replacement policy for the cache memory provides for replacement of data in the first cache portion and the second cache portion.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Zvika Greenfield, Nadav Bonen, Israel Diamand
  • Publication number: 20160350237
    Abstract: Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in the cache memory, perform a lookup operation for the first data element in the volatile memory and in response to a failed lookup operation, to generate a cache scrub hint forward the cache scrub hint to a cache scrub engine and identify one or more cache lines to scrub based at least in part on the cache scrub hint. Other examples are also disclosed and claimed.
    Type: Application
    Filed: May 26, 2015
    Publication date: December 1, 2016
    Applicant: Intel Corporation
    Inventors: Aravindh V. Anantaraman, Zvika Greenfield, Israel Diamand, Anant V. Nori, Pradeep Ramachandran, Nir Misgav