Patents by Inventor Itay Poleg

Itay Poleg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10360092
    Abstract: A hybrid approach using hardware and software is used for report management in peripheral component interconnect (PCI) express devices. The device hardware detects an error associated with a transaction with a host computer. The device software identifies a function associated with the error and determines various attributes of the error. The device software then exposes the attributes of the error in the PCI express and the advanced error reporting (AER) capabilities. The error can be reported in a message transaction to the host computer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: July 23, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Hani Ayoub, Adi Habusha, Itay Poleg
  • Patent number: 9928207
    Abstract: Provided are systems and methods for generating transactions with a configurable port. In some implementations, a peripheral device is provided. The peripheral device comprises a configurable port. In some implementations, the configurable port may be configured to receive a first transaction. In these implementations, the first transactions may include an address. The address may include a transaction attribute. In some implementations, the configurable port may extract the transaction attribute and a transaction address from the address. The configurable port may further generate a second transaction that includes the transaction attribute and the transaction address. The configurable port may also transmit the second transaction.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 27, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Adi Habusha, Nafea Bshara, Itay Poleg, Erez Izenberg, Guy Nakibly, Matthew Shawn Wilson
  • Patent number: 8024597
    Abstract: The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violations in device under test designs comprising two different clock domains where the fast clock rate is an integer multiple of the slow clock rate by inserting undefined (i.e., invalid) values on slow clock domain signals during the clock periods when the signals are not supposed to be captured. The undefined values are contained in the logic cone and emulate timing uncertainty of the path. Propagation of the undefined values through the capturing latch indicates improper clock domains crossing handling.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Etai Adar, Ilya Granovsky, Efrat Greenberg, Itay Poleg
  • Publication number: 20090217075
    Abstract: The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violation in device under test designs comprising two different clock domains where the fast clock is an integer multiple of the slow clock by inserting undefined (i.e., invalid) values on slow clock domain signals during the clock periods when the signals are not supposed to be captured. The undefined values are contained in the logic cone and emulate timing uncertainly of the path. Propagation of the undefined values through the capturing latch indicates improper clock domains crossing handling.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 27, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Etai Adar, Ilya Granovsky, Efrat Greenberg, Itay Poleg