Patents by Inventor Iva MAJETICOVA

Iva MAJETICOVA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240201859
    Abstract: A controller of a storage device receives a stream of data from a host system. The stream of data corresponds to logical block addresses. The controller writes the stream of data to data block(s) in a device memory, each data block including respective super word line(s), each super word line including respective word line(s), and each word line corresponding to at least one logical block address. The controller generates a table for storing the logical block addresses in the order of data arrival. In response to receiving an update to one or more logical block addresses of the data block(s), the controller defragments at least one data block, based on the one or more logical block addresses, and writes data for one or more super word lines of the at least one data block to a new data block, based on the table, to retain the order.
    Type: Application
    Filed: July 14, 2023
    Publication date: June 20, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Leeladhar AGARWAL, Dhanunjaya Rao GORRLE, Iva MAJETICOVA