Abstract: Apparatuses for processing substrates are provided herein. Apparatuses include a plasma etch chamber having a showerhead and pedestal for holding a substrate having silicon nitride, at least one outlet for coupling to a vacuum, a solid non-functional silicon source, and a plasma generator. A solid silicon source may be upstream of a substrate, such as at or near a showerhead of a process chamber, or in a remote plasma generator. Apparatuses also include a plasma etch chamber, at least one outlet, a solid non-functional silicon source, a plasma generator, and a controller for controlling operations including instructions for causing introduction of a fluorinating gas and causing ignition of a plasma to form fluorine-containing etching species in the plasma etch chamber.

Abstract: The embodiments herein relate to methods and apparatus for performing ion etching on a semiconductor substrate, as well as methods for forming such apparatus. In some embodiments, an electrode assembly may be fabricated, the electrode assembly including a plurality of electrodes having different purposes, with each electrode secured to the next in a mechanically stable manner. Apertures may be formed in each electrode after the electrodes are secured together, thereby ensuring that the apertures are well-aligned between neighboring electrodes. In some cases, the electrodes are made from degeneratively doped silicon, and the electrode assembly is secured together through electrostatic bonding. Other electrode materials and methods of securing may also be used. The electrode assembly may include a hollow cathode emitter electrode in some cases, which may have a frustoconical or other non-cylindrical aperture shape. A chamber liner and/or reflector may also be present in some cases.

Abstract: Methods of selectively etching silicon nitride on a semiconductor substrate by providing silicon to the plasma to achieve high etch selectivity of silicon nitride to silicon-containing materials are provided. Methods involve providing silicon from a solid or fluidic silicon source or both. A solid silicon source may be upstream of a substrate, such as at or near a showerhead of a process chamber, or in a remote plasma generator. A silicon gas source may be flowed to the plasma during etch.

Abstract: One process used to remove material from a surface is ion etching. In certain cases, ion etching involves delivery of both ions and a reactive gas to a substrate. The disclosed embodiments permit local high pressure delivery of reactive gas to a substrate while maintaining a much lower pressure on portions of the substrate that are outside of the local high pressure delivery area. In many cases, the low pressure is achieved by providing an injection head that confines the high pressure reactant delivery to a small area and vacuums away excess reactants and byproducts as they leave this small area and before they enter the larger substrate processing region. The disclosed injection head may be used to increase throughput while minimizing deleterious collisions between ions and other species present in the substrate processing region. The disclosed injection head may also be used in other types of semiconductor wafer processing.

Abstract: The embodiments herein relate to methods and apparatus for etching features in semiconductor substrates. In a number of cases, the features may be etched while forming a spin-torque-transfer random access memory (STT-RAM) device. In various embodiments, the substrate may be cooled to a low temperature via a cooled substrate support during particular processing steps. The cooled substrate support may have beneficial impacts in terms of reducing the degree of diffusion-related damage in a resulting device. Further, the use of a non-cooled substrate support during certain other processing steps can likewise have beneficial impacts in terms of reducing diffusion-related damage, depending on the particular step. In some implementations, the cooled substrate support may be used in a process to preferentially deposit a material (in some cases a reactant) on certain portions of the substrate. The disclosed embodiments may be used to achieve high quality anisotropic etching results.

Abstract: One process that may be used to remove material from a surface is ion etching. In certain cases, ion etching involves delivery of both ions and a reactive gas to a substrate. The disclosed embodiments permit local high pressure delivery of reactive gas to a substrate while maintaining a much lower pressure on portions of the substrate that are outside of the local high pressure delivery area. The low pressure is achieved by confining the high pressure reactant delivery to a small area and vacuuming away excess reactants and byproducts as they leave this small area and before they enter the larger substrate processing region. The disclosed techniques may be used to increase throughput while minimizing deleterious collisions between ions and other species present in the substrate processing region.

Abstract: One system includes a chamber, a chuck assembly, and an ion source. The chuck assembly includes a substrate support and a precession assembly with a center support coupled to a stationary center point of an under region of the substrate support. The precession assembly includes first and second actuators connected to first and second locations, respectively, that are in the under region off-set from the center point. The precession assembly imparts a precession motion to the substrate support when the first actuator and the second actuator move up and down relative to the center support, and the precession motion imparted to the substrate causes a rotating tilt of the substrate support without rotation of the substrate support. The rotating tilt of the substrate is configured to cause ions generated by the ion source to impinge upon a surface of the substrate in continually varying angles of incidence.

Abstract: One system includes a chamber, a chuck assembly, and an ion source. The chuck assembly includes a substrate support and a precession assembly with a center support coupled to a stationary center point of an under region of the substrate support. The precession assembly includes first and second actuators connected to first and second locations, respectively, that are in the under region off-set from the center point. The precession assembly imparts a precession motion to the substrate support when the first actuator and the second actuator move up and down relative to the center support, and the precession motion imparted to the substrate causes a rotating tilt of the substrate support without rotation of the substrate support. The rotating tilt of the substrate is configured to cause ions generated by the ion source to impinge upon a surface of the substrate in continually varying angles of incidence.

Abstract: The embodiments herein relate to methods and apparatus for etching features in semiconductor substrates. In a number of cases, the features may be etched while forming a spin-torque-transfer random access memory (STT-RAM) device. In various embodiments, the substrate may be cooled to a low temperature via a cooled substrate support during particular processing steps. The cooled substrate support may have beneficial impacts in terms of reducing the degree of diffusion-related damage in a resulting device. Further, the use of a non-cooled substrate support during certain other processing steps can likewise have beneficial impacts in terms of reducing diffusion-related damage, depending on the particular step. In some implementations, the cooled substrate support may be used in a process to preferentially deposit a material (in some cases a reactant) on certain portions of the substrate. The disclosed embodiments may be used to achieve high quality anisotropic etching results.

Abstract: The embodiments herein relate to methods and apparatus for etching features in semiconductor substrates. In a number of cases, the features may be etched while forming a spin-torque-transfer random access memory (STT-RAM) device. In various embodiments, the substrate may be cooled to a low temperature via a cooled substrate support during particular processing steps. The cooled substrate support may have beneficial impacts in terms of reducing the degree of diffusion-related damage in a resulting device. Further, the use of a non-cooled substrate support during certain other processing steps can likewise have beneficial impacts in terms of reducing diffusion-related damage, depending on the particular step. In some implementations, the cooled substrate support may be used in a process to preferentially deposit a material (in some cases a reactant) on certain portions of the substrate. The disclosed embodiments may be used to achieve high quality anisotropic etching results.

Abstract: Systems and methods for processing a substrate include exposing a substrate to UV light from a UV light source having a predetermined wavelength range. The substrate includes a photoresist layer that has been bombarded with ions. The method includes controlling a temperature of the substrate, while exposing the substrate to the UV light, to a temperature less than or equal to a first temperature. The method includes removing the photoresist layer using plasma while maintaining a temperature of the substrate to less than or equal to a strip process temperature after exposing the substrate to the UV light.

Abstract: Well-controlled, conformal doping of semiconductor substrates may be achieved by low temperature hydrogen-containing plasma treatment prior to gas phase doping. Substrates doped in this manner may be capped and annealed for thermal drive-in of the dopant. The technique is particularly applicable to the formation of ultrashallow junctions (USJs) in three-dimensional (3D) semiconductor structures, such as FinFET and Gate-All-Around (GAA) devices.

Abstract: One system includes a chamber, a chuck assembly, and an ion source. The chuck assembly includes a substrate support and a precession assembly with a center support coupled to a stationary center point of an under region of the substrate support. The precession assembly includes first and second actuators connected to first and second locations, respectively, that are in the under region off-set from the center point. The precession assembly imparts a precession motion to the substrate support when the first actuator and the second actuator move up and down relative to the center support, and the precession motion imparted to the substrate causes a rotating tilt of the substrate support without rotation of the substrate support. The rotating tilt of the substrate is configured to cause ions generated by the ion source to impinge upon a surface of the substrate in continually varying angles of incidence.

Abstract: Disclosed herein are methods of modifying a reaction rate on a semiconductor substrate in a processing chamber which utilize a phased-array of microwave antennas. The methods may include energizing a plasma in a processing chamber, emitting a beam of microwave radiation from a phased-array of microwave antennas, and directing the beam into the plasma so as to cause a change in a reaction rate on the surface of a semiconductor substrate inside the processing chamber. Also disclosed herein are particular embodiments of phased-arrays of microwave antennas, as well as semiconductor processing apparatuses which include a phased-array of microwave antennas configured to emit a beam of microwave radiation into a processing chamber.

Abstract: Various embodiments herein relate to methods and apparatus for performing anisotropic ion beam etching to form arrays of channels. The channels may be formed in semiconductor material, and may be used in a gate-all-around device. Generally speaking, a patterned mask layer is provided over a layer of semiconductor material. Ions are directed toward the substrate while the substrate is positioned in two particular orientations with respect to the ion trajectory. The substrate switches between these orientations such that ions impinge upon the substrate from two opposite angles. The patterned mask layer shadows/protects the underlying semiconductor material such that the channels are formed in intersecting shadowed regions.

Abstract: Various embodiments herein relate to methods and apparatus for performing anisotropic ion beam etching to form arrays of channels. The channels may be formed in semiconductor material, and may be used in a gate-all-around device. Generally speaking, a patterned mask layer is provided over a layer of semiconductor material. Ions are directed toward the substrate while the substrate is positioned in two particular orientations with respect to the ion trajectory. The substrate switches between these orientations such that ions impinge upon the substrate from two opposite angles. The patterned mask layer shadows/protects the underlying semiconductor material such that the channels are formed in intersecting shadowed regions.

Abstract: Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of NO activation of an oxide surface. Once activated, a fluorine-containing gas or vapor etches the activated surface. Etching is self-limiting as once the activated surface is removed, etching stops since the fluorine species does not spontaneously react with the un-activated oxide surface. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where accurate removal of one or multiple atomic layers of material is desired.

Abstract: The embodiments herein relate to methods and apparatus for performing ion etching on a semiconductor substrate, as well as methods for forming such apparatus. In some embodiments, an electrode assembly may be fabricated, the electrode assembly including a plurality of electrodes having different purposes, with each electrode secured to the next in a mechanically stable manner. Apertures may be formed in each electrode after the electrodes are secured together, thereby ensuring that the apertures are well-aligned between neighboring electrodes. In some cases, the electrodes are made from degeneratively doped silicon, and the electrode assembly is secured together through electrostatic bonding. Other electrode materials and methods of securing may also be used. The electrode assembly may include a hollow cathode emitter electrode in some cases, which may have a frustoconical or other non-cylindrical aperture shape. A chamber liner and/or reflector may also be present in some cases.

Abstract: Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of a reaction of anhydrous HF with an activated surface of an oxide, with an emphasis on removal of water generated in the reaction. In certain embodiments the oxide surface is first modified by adsorbing an OH-containing species (e.g., an alcohol) or by forming OH bonds using a hydrogen-containing plasma. The activated oxide is then etched by a separately introduced anhydrous HF, while the water generated in the reaction is removed from the surface of the substrate as the reaction proceeds, or at any time during or after the reaction. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where accurate removal of one or multiple atomic layers of material is desired.

Abstract: Methods of selectively etching silicon nitride on a semiconductor substrate by providing silicon to the plasma to achieve high etch selectivity of silicon nitride to silicon-containing materials are provided. Methods involve providing silicon from a solid or fluidic silicon source or both. A solid silicon source may be upstream of a substrate, such as at or near a showerhead of a process chamber, or in a remote plasma generator. A silicon gas source may be flowed to the plasma during etch.