Patents by Inventor Ivan Leonidovich Mazurenko

Ivan Leonidovich Mazurenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200007159
    Abstract: A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Inventors: Jie JIN, Wen TONG, Jun WANG, Alexander Alexandrovich PETYUSHKO, Ivan Leonidovich MAZURENKO, Chaolong ZHANG
  • Publication number: 20190334559
    Abstract: Provided is a base matrix of a rate-adaptive irregular QC-LDPC code, the base matrix being formed by columns and rows having entries representing circulant submatrices. The columns of the base matrix are divided into at least one or more higher weight first columns and lower weight second columns and the rows of the base matrix are divided into first high weight rows corresponding to the high rate mother code and second low weight rows corresponding to the extension part related to the lower rate codes. A first submatrix formed by an intersection of entries of the second columns and entries of the first and the second rows is divided into first quadratic submatrices, wherein at most one entry in each column of each first submatrix and/or at most one entry in each row of each first submatrix is labelled.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 31, 2019
    Inventors: Pavel Anatolyevich PANTELEEV, Gleb Vyacheslavovich KALACHEV, Ivan Leonidovich MAZURENKO, Elyar Eldarovich GASANOV, Yurii Sergeevich SHUTKIN
  • Publication number: 20190260390
    Abstract: Certain aspects of the present disclosure provide an efficiently decodable QC-LDPC code which is based on a base matrix, the base matrix being formed by columns and rows, the columns being dividable into one or more columns corresponding to punctured variable nodes and columns corresponding to non-punctured variable nodes. Apparatus at a transmitting side includes a encoder configured to encode a sequence of information bits based on the base matrix. Apparatus at a receiving side configured to receive a codeword in accordance with a radio technology across a wireless channel. The apparatus at the receiving side includes a decoder configured to decode the codeword based on the base matrix.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Yurii Sergeevich SHUTKIN, Pavel Anatolyevich PANTELEEV, Aleksey Alexandrovich LETUNOVSKIY, Elyar Eldarovich GASANOV, Gleb Vyacheslavovich KALACHEV, Ivan Leonidovich MAZURENKO
  • Publication number: 20180337691
    Abstract: A decoding method, an encoding method, a decoder and an encoder are disclosed. In an embodiment the decoding method includes receiving, at a receiver of a receiving side, signals from a transmitting side, the signals including a code word and decoding, at a decoder of the receiving side, the code word using a low density parity check (LDPC) code in which each n adjacent rows, n>1, in an extension part of a base parity check matrix (PCM) are orthogonal except for punctured information columns.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 22, 2018
    Inventors: Gleb Vyacheslavovich Kalachev, Ivan Leonidovich Mazurenko, Elyar Eldarovich Gasanov, Carmela Cozzo, Jie Jin
  • Publication number: 20180323802
    Abstract: A method for generating a code, a method for encoding and decoding data, and an encoder and a decoder performing the encoding and decoding are disclosed. In an embodiment, a method for lifting a child code from a base code for encoding and decoding data includes determining a single combination of a circulant size, a lifting function, and a labelled base matrix PCM according to an information length and a code rate using data stored in a lifting table. The lifting table was defined at a code generation stage. The method also includes calculating a plurality of shifts for the child code. Each shift is calculated by applying the lifting function to the labelled base matrix PCM with a defined index using the circulant size and using the derived child PCM to encode or decode data.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 8, 2018
    Inventors: Gleb Vyacheslavovich Kalachev, Ivan Leonidovich Mazurenko, Pavel Anatolyevich Panteleev, Elyar Eldarovich Gasanov, Aleksey Alexandrovich Letunovskiy, Wen Tong, Carmela Cozzo
  • Publication number: 20180226992
    Abstract: A method and system for offset lifting is provided. In an embodiment, a method for encoding data includes receiving a K-bit source word input. The method also includes encoding the K-bit source word input according to a LDPC code, a lifting function, and a circulant size offset to generate an N-bit code word output. The circulant size and lifting function are determined according to an information length, a code rate, and a decoder. The method also includes storing the N-bit code word output in input/output memory.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 9, 2018
    Inventors: Pavel Anatolyevich Panteleev, Wen Tong, Jiang Li, Gleb Vyacheslavovich Kalachev, Ivan Leonidovich Mazurenko, Elyar Eldarovich Gasanov, Aleksey Alexandrovich Letunovskiy
  • Patent number: 9542748
    Abstract: Systems and methods for image processing may perform one or more operations including, but not limited to: receiving raw image data from at least one imaging device; computing at least one image depth distance from the raw image data; computing one or more image validity flags from the raw image data; generating at least one data validity mask from the one or more image validity flags; determining a background imagery estimation from at least one image depth distance; generating at least one foreground mask from the background imagery estimation and the at least one image depth distance; generating at least one region-of-interest mask from the data validity mask and the foreground mask; and generating filtered raw image data from the raw image data and at least one region of interest mask.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: January 10, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ivan Leonidovich Mazurenko, Pavel Aleksandrovich Aliseitchik, Alexander Borisovich Kholodenko, Denis Vasilyevich Parfenov, Denis Vladimirovich Parkhomenko
  • Patent number: 9384556
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a foreground processing module utilizing the image processing circuitry and the memory. The foreground processing module is configured to obtain one or more images, to estimate a foreground region of interest from the one or more images, to determine a plurality of segments of the foreground region of interest, to calculate amplitude statistics for respective ones of the plurality of segments, to classify respective segments as being respective portions of static foreground objects or as being respective portions of dynamic foreground objects based at least in part on the calculated amplitude statistics and one or more defined patterns for known static and dynamic objects, and to remove one or more segments classified as static foreground objects from the foreground region of interest.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: July 5, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ivan Leonidovich Mazurenko, Denis Vladimirovich Parkhomenko, Pavel Aleksandrovich Aliseitchik, Barrett J. Brickner, Dmitry Nicolaevich Babin
  • Patent number: 9362977
    Abstract: In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes non-overlapping chunks of incoming antenna data, where each chunk is smaller than the preamble length, to detect the signature of the transmitted preamble. For each chunk processed, chips of the chunk are correlated with possible signatures employed by the wireless network to update a set of correlation profiles, each profile comprising a plurality of profile values. Further, an intermediate detection is performed by comparing the updated profile values to an intermediate threshold that is also updated for each chunk. Upon receiving the final chunk, the correlation profiles are updated, and a final preamble detection is made by comparing the updated profile values to a final threshold. Detections are performed on an incremental basis to meet latency requirements of the wireless network.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: June 7, 2016
    Assignee: Intel Corporation
    Inventors: Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Meng-Lin Yu, Jian-Guo Chen
  • Patent number: 9336431
    Abstract: A method and system for key frame based region of interest (ROI) tracking is disclosed. The method includes storing a key ROI set in a key ROI buffer, the key ROI set including at least one key ROI; designating one of the key ROI in the key ROI set as an active key ROI; receiving a point cloud representing a particular ROI to be processed for tracking; establishing a correspondence between that particular ROI and the active key ROI; determining whether to switch the active key designation to another key ROI in the key ROI set and switching the active key designation accordingly; and determining whether to modify the key ROI set and modifying the key ROI set accordingly.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: May 10, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Denis Vladimirovich Parkhomenko, Alexander Borisovich Kholodenko, Dmitry Nicolaevich Babin
  • Patent number: 9294128
    Abstract: A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple binary searches on segments. Segments are defined based on codeword, trapping set and biasing noise components of the channel. To improve calculation speed the most significant subclasses of codewords, trapping sets and noise signals are used.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 22, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Denis Vladimirovich Zaytsev, Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Aleksey Alexandrovich Letunovskiy, Pavel Aleksandrovich Aliseitchik, Dmitry Nicolaevich Babin
  • Patent number: 9184787
    Abstract: In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Meng-Lin Yu, Jian-Guo Chen, Alexander Alexandrovich Petyushko, Ivan Leonidovich Mazurenko
  • Publication number: 20150310264
    Abstract: In one embodiment, an image processor comprises image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system utilizing the image processing circuitry and the memory. The gesture recognition system implemented by the image processor comprises a dynamic gesture recognition module. The dynamic gesture recognition module is configured to establish a dynamic gesture recognition interval comprising a plurality of image frames, to extract one or more first features from the dynamic gesture recognition interval, to adjust the dynamic gesture recognition interval, to extract one or more second features from the adjusted dynamic gesture recognition interval, and to recognize a dynamic gesture based at least in part on at least a subset of the extracted first and second features.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 29, 2015
    Inventors: Pavel Aleksandrovich Aliseitchik, Ivan Leonidovich Mazurenko, Aleksey Alexandrovich Letunovskiy, Denis Vasilyevich Parfenov, Denis Vladimirovich Parkhomenko
  • Publication number: 20150302593
    Abstract: Systems and methods for image processing may perform one or more operations including, but not limited to: receiving raw image data from at least one imaging device; computing at least one image depth distance from the raw image data; computing one or more image validity flags from the raw image data; generating at least one data validity mask from the one or more image validity flags; determining a background imagery estimation from at least one image depth distance; generating at least one foreground mask from the background imagery estimation and the at least one image depth distance; generating at least one region-of-interest mask from the data validity mask and the foreground mask; and generating filtered raw image data from the raw image data and at least one region of interest mask.
    Type: Application
    Filed: April 8, 2013
    Publication date: October 22, 2015
    Applicant: LSI Corporation
    Inventors: Ivan Leonidovich Mazurenko, Pavel Aleksandrovich Aliseitchik, Alexander Borisovich Kholodenko, Denis Vasilyevich Parfenov, Denis Vladimirovich Parkhomenko
  • Publication number: 20150278589
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system utilizing the image processing circuitry and the memory. The gesture recognition system implemented by the image processor comprises a static pose recognition module. The static pose recognition module is configured to identify a hand region of interest in at least one image, to determine a contour of the hand region of interest, to triangulate the determined contour, to flatten the triangulated contour, to compute one or more features of the flattened contour, and to recognize a static pose of the hand region of interest based at least in part on the one or more computed features.
    Type: Application
    Filed: March 25, 2015
    Publication date: October 1, 2015
    Inventors: Ivan Leonidovich Mazurenko, Alexander Borisovich Kholodenko, Dmitry Nicolaevich Babin, Aleksey Alexandrovich Letunovskiy, Alexander Alexandrovich Petyushko
  • Publication number: 20150269740
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a foreground processing module utilizing the image processing circuitry and the memory. The foreground processing module is configured to obtain one or more images, to estimate a foreground region of interest from the one or more images, to determine a plurality of segments of the foreground region of interest, to calculate amplitude statistics for respective ones of the plurality of segments, to classify respective segments as being respective portions of static foreground objects or as being respective portions of dynamic foreground objects based at least in part on the calculated amplitude statistics and one or more defined patterns for known static and dynamic objects, and to remove one or more segments classified as static foreground objects from the foreground region of interest.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 24, 2015
    Inventors: Ivan Leonidovich Mazurenko, Denis Vladimirovich Parkhomenko, Pavel Aleksandrovich Aliseitchik, Barrett J. Brickner, Dmitry Nicolaevich Babin
  • Publication number: 20150253864
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system utilizing the image processing circuitry and the memory. The gesture recognition system comprises a finger detection and tracking module configured to identify a hand region of interest in a given image, to extract a contour of the hand region of interest, to detect fingertip positions using the extracted contour, and to track movement of the fingertip positions over multiple images including the given image.
    Type: Application
    Filed: March 6, 2015
    Publication date: September 10, 2015
    Inventors: Denis Vladimirovich Parkhomenko, Ivan Leonidovich Mazurenko, Dmitry Nicolaevich Babin, Denis Vladimirovich Zaytsev, Aleksey Alexandrovich Letunovskiy
  • Publication number: 20150253863
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system comprising a static pose recognition module. The static pose recognition module is configured to identify a hand region of interest in at least one image, to obtain a vocabulary of hand poses, to estimate a plurality of hand features based on the hand region of interest, the plurality of hand features comprising a first set of features estimated from the hand region of interest and a second set of features comprising at least one feature estimated using a transform on a contour of the hand region of interest, and to recognize a static pose of the hand region of interest based on the first set of features and the second set of features, wherein respective numbers of features in the first set of features and the second set of features are based at least in part on a size of the vocabulary of hand poses.
    Type: Application
    Filed: March 6, 2015
    Publication date: September 10, 2015
    Inventors: Dmitry Nicolaevich Babin, Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Aleksey Alexandrovich Letunovskiy, Denis Vladimirovich Zaytsev
  • Patent number: 9037944
    Abstract: A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 19, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Alexander Alexandrovich Petyushko, Anatoli Aleksandrovich Bolotov, Yang Han, Ivan Leonidovich Mazurenko, Alexander Borisovich Kholodenko, Denis Vladimirovich Zaytsev, Denis Vasilievich Parfenov
  • Patent number: 8977925
    Abstract: A method for ordering trapping sets to find one or more dominant trapping sets includes analyzing a trapping set and a random set of codewords to generate a distance value for each trapping set, and ordering the trapping sets by the distance value. Distance values may be determined for each trapping set by tracking a vote count wherein a correct decode at a certain noise level produces a “right” vote and an incorrect decode at a certain noise level produces a “left” vote. A certain threshold number of “left” votes terminates processing at that noise level.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: March 10, 2015
    Assignee: LSI Corporation
    Inventors: Denis Vladimirovich Zaytsev, Denis Vasilievich Parfenov, Yang Han, Ivan Leonidovich Mazurenko, Dmitry Nicolaevich Babin