Abstract: Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.

Abstract: A presence detectable baffle for electrical components in a computing system, including: a passive chassis having a form factor is consistent with an electrical component of the computing system; and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component.

Abstract: A presence detectable baffle for electrical components in a computing system, including: a passive chassis having a form factor is consistent with an electrical component of the computing system; and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component.

Abstract: Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.

Abstract: Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.

Abstract: Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.

Abstract: Methods, apparatus, and products for reliable memory mapping in a computing system, the computing system including a plurality of memory modules, including: determining, by a channel mapping module, a reliability rating for each of a plurality of memory controller address ranges; mapping, by the channel mapping module, critical system-level memory addresses to the most reliable memory controller address ranges; and directing, by the channel mapping module, memory accesses addressed to a critical system-level memory address to the most reliable memory controller address ranges.

Abstract: A method, computer program product and system for controlling the maximum turbo mode of a processor in a turbo boost state. The method comprises limiting a maximum turbo mode available to the processor by over-reporting the amount of current drawn by the processor to the current monitoring feedback line to the processor, wherein the processor uses the over-reported current to maintain operation of the processor within performance specifications of the processor. An automatic calibration routine may be used to determine nominal amounts of current over-reporting that may be used to prevent the processor performance from exceeding the maximum turbo mode. In one embodiment, a digital potentiometer is included in the voltage regulator circuit to over-report the current as instructed.

Abstract: A presence detectable baffle for electrical components in a computing system, including: a passive chassis having a form factor is consistent with an electrical component of the computing system; and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component.

Abstract: Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.

Abstract: A presence detectable baffle for electrical components in a computing system, including: a passive chassis having a form factor is consistent with an electrical component of the computing system; and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component.

Abstract: Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.

Abstract: One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.

Abstract: One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.

Abstract: Method and apparatus providing airflow through a chassis including an upstream column of memory modules and a downstream column of memory modules. The airflow is divided into first and second separate airflow streams extending from an upstream end of the upstream column to a downstream end of the downstream column. The first airflow stream is guided into contact with a single memory module operably-installed in the upstream column and to avoid contact with any memory module in the downstream column. The second airflow stream is guided to avoid contact with any memory module in the upstream column and into contact with a single memory module operably-installed in the downstream column. The improved cooling enables the extended use of a single memory module per channel, even though the thermal load on such a memory module is greater.

Abstract: A method, computer program product and system for controlling the maximum turbo mode of a processor in a turbo boost state. The method comprises limiting a maximum turbo mode available to the processor by over-reporting the amount of current drawn by the processor to the current monitoring feedback line to the processor, wherein the processor uses the over-reported current to maintain operation of the processor within performance specifications of the processor. An automatic calibration routine may be used to determine nominal amounts of current over-reporting that may be used to prevent the processor performance from exceeding the maximum turbo mode. In one embodiment, a digital potentiometer is included in the voltage regulator circuit to over-report the current as instructed.

Abstract: Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time.

Abstract: Methods, apparatus, and products are disclosed for preemptive thermal management for a computing system based on cache performance, the computing system having a processor, cached computer memory operatively coupled to the processor, and a processor cache operatively coupled to the processor, the processor cache capable of storing a subset of memory contents of the cached computer memory, that include: attempting, by the processor, to retrieve portions of the memory contents of the cached computer memory from the processor cache, resulting in cache misses for the processor cache; tracking, by the processor, cache miss statistics for the processor cache in the computing system, the cache miss statistics describing the cache misses for the processor cache; and administering a thermal management device for the computing system in dependence upon the cache miss statistics, the thermal management device operatively coupled to the processor and capable of managing temperature for the computing system.

Abstract: Method and apparatus providing airflow through a chassis including an upstream column of memory modules and a downstream column of memory modules. The airflow is divided into first and second separate airflow streams extending from an upstream end of the upstream column to a downstream end of the downstream column. The first airflow stream is guided into contact with a single memory module operably-installed in the upstream column and to avoid contact with any memory module in the downstream column. The second airflow stream is guided to avoid contact with any memory module in the upstream column and into contact with a single memory module operably-installed in the downstream column. The improved cooling enables the extended use of a single memory module per channel, even though the thermal load on such a memory module is greater.

Abstract: An embodiment of the present invention is directed to a memory module connector having a pivotable air baffle that controls airflow at the memory module connector. When the memory module connector is occupied by a memory module, the air baffle may rest on an upper edge of the memory module, substantially parallel to the system board and in general alignment with the airflow. When the memory module has been removed, the air baffle may be pivoted downward toward the connector base and into the airflow, to offset the reduction in airflow impedance caused by the removal of the memory module from the memory module connector.