Abstract: A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.

Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process transfers to/from a medium. The control circuit may be configured to generate a trapping set list of trapping sets of a low-density parity check code, classify bit positions of the trapping sets as belonging to either a user bits field or a parity bits field of a codeword, encode data using the low-density parity check code to generate the codeword, and present the codeword to the interface to transfer the codeword to the medium. The generation of the codeword may include at least one of a shortening or a puncturing of bit locations in the codeword in response to the classifying of the bit positions of the trapping sets. All of the data may be held in the bit locations of the codeword other than the bit locations that are shortened or punctured.

Abstract: Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.

Abstract: An apparatus having an interface and a control circuit is disclosed. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to (i) access information that characterizes a plurality of trapping sets of a low-density parity check code in response to receiving data, (ii) encode the data using the low-density parity check code to generate a codeword and (iii) write the codeword in the memory. The generation of the codeword may include at least one of a shortening and a puncturing of a plurality of bits in the codeword. The plurality of bits may be selected based on the information that characterizes the plurality of trapping sets. The bits selected generally reduce a probability that an error correction of the codeword after the codeword is read from the memory fails due to the plurality of trapping sets.

Abstract: Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.

Abstract: An electronic non-volatile computer storage apparatus and methods for reducing decoder error floor for such a storage apparatus are disclosed. An analysis process it utilized to study one or more performance metrics of a decoder of the storage apparatus in order to determine various endurance points throughout the lifetime of that particular type of storage apparatus. Theses endurance points indicate when different scaling factors should be applied and/or when log-likelihood ratio should be re-measured to accommodate physical degradations over time.

Abstract: An apparatus includes a plurality of memory dies and a controller. The controller may be communicatively coupled to the plurality of memory dies and configured to utilize multiple copies of a root record containing system data during a boot-up process. The multiple copies of the root record are stored using at least two of the plurality of memory dies.

Abstract: An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.

Abstract: An apparatus includes a plurality of memory dies and a controller. The controller may be communicatively coupled to the plurality of memory dies and configured to utilize multiple copies of a root record containing system data during a boot-up process. The multiple copies of the root record are stored using at least two of the plurality of memory dies.

Abstract: An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.

Abstract: A method and system for constructing a generator matrix is disclosed. The method includes: receiving a parity check matrix H, wherein the parity check matrix H includes multiple circulant sub-matrices; rearranging the parity check matrix H by column and row permutations to obtain a rearranged parity check matrix H?; and constructing the generator matrix G based on the rearranged parity check matrix H?.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reducing inter-track interference in relation to processing data retrieved from a storage medium.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for adapting noise predictive filters for inter-track interference cancellation in a data processing system.

Abstract: A method and system for constructing a generator matrix is disclosed. The method includes: receiving a parity check matrix H, wherein the parity check matrix H includes multiple circulant sub-matrices; rearranging the parity check matrix H by column and row permutations to obtain a rearranged parity check matrix H?; and constructing the generator matrix G based on the rearranged parity check matrix H?.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for adapting noise predictive filters for inter-track interference cancellation in a data processing system.

Abstract: The present invention relates to a novel method for the biocatalytic production of unsaturated dicarboxylic acids by cultivating a recombinant microorganism co-expressing a glutaconate CoA-transferase and a 2-hydroxyglutaryl-CoA dehydratase system. The present invention also relates to corresponding recombinant hosts, recombinant vectors, expression cassettes and nucleic acids suitable for preparing such hosts as well as a method of preparing polyamide or polyester copolymers making use of said dicarboxylic acids as obtained by said biocatalytic production method.

Abstract: A circuit and method form a codeword including parity and message bits, as follows. Each codeword has a first part in a current sequence (e.g. a current OTN-row) that is to be now transmitted and second part spread across multiple past sequences (e.g. previously prepared and transmitted OTN-rows). The codewords are grouped into multiple groups such that each codeword within a group has no bit in common with another codeword in that group. Moreover, each codeword has a bit in common with a different codeword in a different group.

Abstract: Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information.

Abstract: Flash memory devices and associated methods are described for controlling data errors in the devices through various forms of decoding, error correction, and wear concentration. To this end, a flash memory device may be partitioned into a plurality of sectors. Data may then be received from, for example, a host processor for storage within the flash memory device. Storage durations of the data are then estimated and the data is stored in the data sectors based on those estimated storage durations.

Abstract: A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.