Abstract: Systems and methods for hardware-based asynchronous logging include: initiating first and second atomic regions on first and second cores of a central processing unit (CPU); and asynchronously logging data for the first atomic region and the second atomic region using the CPU by: asynchronously performing log persist operations (LPOs) to log an old data value from each atomic region; updating the old data value to a new data value from each atomic region; tracking dependencies between the first atomic region and the second atomic region using a memory controller; asynchronously performing data persist operations (DPOs) to persist the new data value for each atomic region; and committing the first atomic region and the second atomic region based on the dependencies using the memory controller of the CPU.

Abstract: Techniques for a thread in client process to switch to a server virtual address space are provided. In one aspect, a process may attach to a server virtual address space. A request may be received from a client thread within the client process to switch from a virtual address space associated with the client thread to a server virtual address space. The client thread may switch from the client thread associated virtual address space to the server virtual address space.

Abstract: Example implementations relate to persistent virtual address spaces. In one example, persistent virtual address spaces can employ a non-transitory processor readable medium including instructions to receive a whole data structure of a virtual address space (VAS) associated with a process, where the whole data structure includes data and metadata of the VAS, and store the data and the metadata of the VAS in a non-volatile memory to form a persistent VAS (PVAS).

Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.

Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.

Abstract: Techniques for a thread in client process to switch to a server virtual address space are provided. In one aspect, a process may attach to a server virtual address space. A request may be received from a client thread within the client process to switch from a virtual address space associated with the client thread to a server virtual address space. The client thread may switch from the client thread associated virtual address space to the server virtual address space.

Abstract: Example implementations relate to persistent virtual address spaces. In one example, persistent virtual address spaces can employ a non-transitory processor readable medium including instructions to receive a whole data structure of a virtual address space (VAS) associated with a process, where the whole data structure includes data and metadata of the VAS, and store the data and the metadata of the VAS in a non-volatile memory to form a persistent VAS (PVAS).