Abstract: Provided herein are improved compounds, compositions and associated methods for reducing expression of ApoCIII mRNA and protein in a subject having, or at risk of having, diabetes. Also provided herein are compounds, compositions and associated methods improving peripheral insulin sensitivity, a lipid profile and a diabetes profile as well as reducing free fatty acids and intramyocellular triglyceride deposition.

Abstract: Anthropometric measurements provide indicators of human and livestock health and wellbeing. Today, there is a well-developed manual protocol to measure the proportionate size of humans but it is slow, requires bulky and costly equipment, is subject to accuracy and precision errors, and requires initial and on-going training of field staff. There are also techniques to measure animal size but they generally require fixed installations and multiple imagers. Portable 3-D imaging systems in conjunction with portable computing devices and access to the cloud computing and storage infrastructure will be useful tools to automatically, objectively extract these anthropometric measures, and to consistently provide other anthropometric measures which heretofore have been unobtainable, provided the difficulty of scanning moving subjects can be overcome.

Abstract: Technical solutions are described for authenticating a hosting system prior to securely deploying a shrouded virtual server. An example method includes receiving, by a hypervisor, a request for a public certificate, from a client device that requested the virtual server, and sending the public certificate of the hosting system that executes the hypervisor. The method also includes receiving, in response to the public certificate being successfully authenticated by the client device using a third-party verification system, a session key based on a public key included in the public certificate. The method also includes decrypting the session key using a private key, where the private key is pre-installed in the hosting system by a manufacturer of the hosting system, and sending an acknowledgement message encrypted using the session key. The method also includes establishing a secure communication between the client device and the hypervisor using the session key.

Abstract: A load-conveying and transport apparatus includes a first frame, a conveyor carried by the first frame, and a second frame mounted to the first frame for movement between lowered and raised positions relative to the conveyor. The second frame lies below the conveyor, when the second frame is in the lowered position relative to the conveyor. The second frame lies proud of the conveyor, when the second frame is in the raised position relative to the conveyor. The conveyor is for conveying a load placed thereon without interference from the second frame, when the second frame is in the lowered position relative to the conveyor. The second frame is for supporting the load placed thereon above the conveyor for disabling the conveyor from conveying the load, when the second frame is in the raised position.

Abstract: Technical solutions are described for securely deploying a shrouded virtual server. An example method includes sending, by a host manager, authentication information of a hosting system to a client device in response to a request from the client device. The \method also includes receiving a request to deploy a virtual server using a shrouded mode. The method also includes deploying a preconfigured hypervisor on the hosting system, where the preconfigured hypervisor is deployed in an immutable mode that disables changes to security settings of the preconfigured hypervisor. The method also includes deploying, by the preconfigured hypervisor, a preconfigured boot image as an instance of the virtual server on the preconfigured hypervisor. The method also includes sending, by the host manager, an identifier of the virtual server for receipt by the client device.

Abstract: The present disclosure is applicable to all vehicles having an engine mounted therein. In one embodiment, an aft mount system for a gas turbine engine is disclosed. The aft mount system includes a vehicle chassis and at least one flexible mounting member disposed within the vehicle chassis, wherein when a gas turbine engine is received within the vehicle chassis, an exhaust portion of the gas turbine engine is substantially mounted within the vehicle chassis through engagement with the at least one flexible mounting member.

Abstract: A load-conveying and transport apparatus includes a first frame, a conveyor carried by the first frame, and a second frame mounted to the first frame for movement between lowered and raised positions relative to the conveyor. The second frame lies below the conveyor, when the second frame is in the lowered position relative to the conveyor. The second frame lies proud of the conveyor, when the second frame is in the raised position relative to the conveyor. The conveyor is for conveying a load placed thereon without interference from the second frame, when the second frame is in the lowered position relative to the conveyor. The second frame is for supporting the load placed thereon above the conveyor for disabling the conveyor from conveying the load, when the second frame is in the raised position.

Abstract: Techniques for generating a design structure for cache power reduction are described herein. In one example, a system includes logic to detect memory address information corresponding to accessed data in a first instruction, and detect memory address information corresponding to accessed data in a second instruction. The logic can also compare the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detect, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. The logic can also execute the second instruction using the accessed data from the first instruction.

Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises detecting memory address information corresponding to accessed data in a first instruction, and detecting memory address information corresponding to accessed data in a second instruction. The method further comprises comparing the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detecting, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. In addition the method comprise executing the second instruction using the accessed data from the first instruction and detecting an error from the execution of the second instruction.

Abstract: Technical solutions are described for authenticating a hosting system prior to securely deploying a shrouded virtual server. An example method includes receiving, by a hypervisor, a request for a public certificate, from a client device that requested the virtual server, and sending the public certificate of the hosting system that executes the hypervisor. The method also includes receiving, in response to the public certificate being successfully authenticated by the client device using a third-party verification system, a session key based on a public key included in the public certificate. The method also includes decrypting the session key using a private key, where the private key is pre-installed in the hosting system by a manufacturer of the hosting system, and sending an acknowledgement message encrypted using the session key. The method also includes establishing a secure communication between the client device and the hypervisor using the session key.

Abstract: A mechanism for simultaneous multithreading is provided. Responsive to performing a store instruction for a given thread of threads on a processor core and responsive to the core having ownership of a cache line in a cache, an entry of the store instruction is placed in a given store queue belonging to the given thread. The entry for the store instruction has a starting memory address and an ending memory address on the cache line. The starting memory addresses through ending memory addresses of load queues of the threads are compared on a byte-per-byte basis against the starting through ending memory address of the store instruction. Responsive to one memory address byte in the starting through ending memory addresses in the load queues overlapping with a memory address byte in the starting through ending memory address of the store instruction, the threads having the one memory address byte is flushed.

Abstract: Embodiments relate to load queue entry reuse for operand store compare (OSC) history table update. An aspect includes allocating a load queue entry in a load queue to a load instruction that is issued into an instruction pipeline, the load queue entry comprising a valid tag that is set and a keep tag that is unset. Another aspect includes based on the flushing of the load instruction, unsetting the valid tag and setting the keep tag. Another aspect includes reissuing the load instruction into the instruction pipeline. Another aspect includes based on determining that the allocated load queue entry corresponds to the reissued load instruction, setting the valid tag and leaving the keep tag set. Another aspect includes based on completing the reissued load instruction, and based on the valid tag and the keep tag being set, updating the OSC history table corresponding to the load instruction.

Abstract: As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.

Abstract: Provided herein are improved compounds, compositions and associated methods for reducing expression of ApoCIII mRNA and protein in a subject having, or at risk of having, diabetes. Also provided herein are compounds, compositions and associated methods improving peripheral insulin sensitivity, a lipid profile and a diabetes profile as well as reducing free fatty acids and intramyocellular triglyceride deposition.

Abstract: Technical solutions are described for authenticating a hosting system prior to securely deploying a shrouded virtual server. An example method includes receiving, by a hypervisor, a request for a public certificate, from a client device that requested the virtual server, and sending the public certificate of the hosting system that executes the hypervisor. The method also includes receiving, in response to the public certificate being successfully authenticated by the client device using a third-party verification system, a session key based on a public key included in the public certificate. The method also includes decrypting the session key using a private key, where the private key is pre-installed in the hosting system by a manufacturer of the hosting system, and sending an acknowledgement message encrypted using the session key. The method also includes establishing a secure communication between the client device and the hypervisor using the session key.

Abstract: Technical solutions are described for securely deploying a shrouded virtual server. An example method includes sending, by a host manager, authentication information of a hosting system to a client device in response to a request from the client device. The \method also includes receiving a request to deploy a virtual server using a shrouded mode. The method also includes deploying a preconfigured hypervisor on the hosting system, where the preconfigured hypervisor is deployed in an immutable mode that disables changes to security settings of the preconfigured hypervisor. The method also includes deploying, by the preconfigured hypervisor, a preconfigured boot image as an instance of the virtual server on the preconfigured hypervisor. The method also includes sending, by the host manager, an identifier of the virtual server for receipt by the client device.

Abstract: A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.

Abstract: A mechanism for simultaneous multithreading is provided. Responsive to performing a store instruction for a given thread of threads on a processor core and responsive to the core having ownership of a cache line in a cache, an entry of the store instruction is placed in a given store queue belonging to the given thread. The entry for the store instruction has a starting memory address and an ending memory address on the cache line. The starting memory addresses through ending memory addresses of load queues of the threads are compared on a byte-per-byte basis against the starting through ending memory address of the store instruction. Responsive to one memory address byte in the starting through ending memory addresses in the load queues overlapping with a memory address byte in the starting through ending memory address of the store instruction, the threads having the one memory address byte is flushed.

Abstract: A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.