Patents by Inventor Jack Chinho Wu
Jack Chinho Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10942873Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.Type: GrantFiled: July 9, 2019Date of Patent: March 9, 2021Assignee: Micron Technology, Inc.Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
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Publication number: 20200012606Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.Type: ApplicationFiled: July 9, 2019Publication date: January 9, 2020Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
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Patent number: 10387338Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.Type: GrantFiled: March 27, 2018Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
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Publication number: 20180285287Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.Type: ApplicationFiled: March 27, 2018Publication date: October 4, 2018Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
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Patent number: 9959220Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.Type: GrantFiled: March 20, 2017Date of Patent: May 1, 2018Assignee: MICRON TECHNOLOGY, INCInventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
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Publication number: 20170192911Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.Type: ApplicationFiled: March 20, 2017Publication date: July 6, 2017Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
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Patent number: 9626292Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.Type: GrantFiled: June 27, 2016Date of Patent: April 18, 2017Assignee: MICRON TECHNOLOGY, INC.Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
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Publication number: 20160306740Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
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Patent number: 9406362Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.Type: GrantFiled: June 17, 2013Date of Patent: August 2, 2016Assignee: MICRON TECHNOLOGY, INC.Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
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Publication number: 20140372713Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.Type: ApplicationFiled: June 17, 2013Publication date: December 18, 2014Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu