Abstract: A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.

Abstract: In a first embodiment of the present invention, a non-blocking switch fabric is provided comprising: a first set of intra-domain switches; a second set of intra-domain switches; a set of inter-domain switches located centrally between the first set of intra-domain switches and the second set of intra-domain switches, wherein each of the ports of each of the inter-domain switches is connected to an intra-domain switch from the first or second set of intra-domain switches.

Abstract: In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I/O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset.

Abstract: In a first embodiment of the present invention, a non-blocking switch fabric is provided comprising: a first set of intra-domain switches; a second set of intra-domain switches; a set of inter-domain switches located centrally between the first set of intra-domain switches and the second set of intra-domain switches, wherein each of the ports of each of the inter-domain switches is connected to an intra-domain switch from the first or second set of intra-domain switches.

Abstract: In a first embodiment of the present invention, a method for error-correcting in a parallel interconnect transmitting device is provided, the method comprising: detecting a frame transition in a transmission from the transmitting device to a parallel interconnect receiving device; tracking time between the frame transition and a transition of a response signal corresponding to the frame transition received from the receiving device; detecting an error in the transmission; and restarting a portion of the transmission in response to the error, wherein the size of the portion of the transmission to restart is based upon the tracked time between the frame transition and the transition of a response signal corresponding to the frame transition.

Abstract: In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I/O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset.

Abstract: A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.

Abstract: A system for communication on a chip. The system includes an on-chip communication bus including plural tracks, and a plurality of stations that couple a plurality of on-chip components to the on-chip communication bus, whereby the plurality of on-chip components use the tracks to communicate. Each station preferably includes an initiator that requests permission to transmit outgoing data over a track to another station and that transmits the outgoing data, an arbiter that evaluates requests from other stations and selects a track on which to receive incoming data, and a target that receives the incoming data. The initiator can be connected to a grant multiplexor for selecting a grant line, with the grant multiplexor further including plural smaller multiplexors distributed across the chip. Likewise, the arbiter can be connected to a track multiplexor for selecting a track, with the track multiplexor further including plural smaller multiplexors distributed across the chip.

Abstract: The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.

Abstract: The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it the cell is retransmitted. The node responds to the transaction sub-action by manipulating shared handshake lines that are bussed with the other nodes. The invention enables snooping cache protocols to be successfully used in a larger multi-processor computer system than the prior art.

Abstract: The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it the cell is retransmitted. The node responds to the transaction sub-action by manipulating shared handshake lines that are bussed with the other nodes. The invention enables snooping cache protocols to be successfully used in a larger multi-processor computer system than the prior art.

Abstract: The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.

Abstract: The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.

Abstract: The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.