Abstract: A transistor diagnostic circuit includes a protection transistor output terminal, a fault terminal, and circuitry coupled to the protection transistor output terminal and the fault terminal. The protection transistor output terminal is adapted to be coupled to a current terminal of a protection transistor. The transistor diagnostic circuit is configured to, at start-up, load the protection transistor output terminal to test the protection transistor, and to generate a fault signal at the fault terminal responsive to a voltage on the protection transistor output terminal exceeding a threshold.

Abstract: A transistor diagnostic circuit includes a protection transistor output terminal, a fault terminal, and circuitry coupled to the protection transistor output terminal and the fault terminal. The protection transistor output terminal is adapted to be coupled to a current terminal of a protection transistor. The transistor diagnostic circuit is configured to, at start-up, load the protection transistor output terminal to test the protection transistor, and to generate a fault signal at the fault terminal responsive to a voltage on the protection transistor output terminal exceeding a threshold.

Abstract: A phase detection system (100) comprises an input terminal (101), first and second peak detectors (103, 113), an averaging unit (107), an offset unit (122), and a comparator (126). Input terminal (101) is coupled to the first and to the second peak detectors (103, 113) and provides an input signal to phase detection system (100). Averaging unit (107) is coupled between offset unit (122) and both the first peak detector and the second peak detector (103, 113), and generates an intermediate signal. Offset unit (122) is coupled to input terminal (101) and generates two comparable signals by applying a predetermined offset in signal strength to the input signal or the intermediate signal. The comparator (126) is coupled to the offset unit (122) and generates an output signal by comparing the two comparable signals which is indicative of the phase of the input signal.

Abstract: A phase detection system (100) comprises an input terminal (101), first and second peak detectors (103, 113), an averaging unit (107), an offset unit (122), and a comparator (126). Input terminal (101) is coupled to the first and to the second peak detectors (103, 113) and provides an input signal to phase detection system (100). Averaging unit (107) is coupled between offset unit (122) and both the first peak detector and the second peak detector (103, 113), and generates an intermediate signal. Offset unit (122) is coupled to input terminal (101) and generates two comparable signals by applying a predetermined offset in signal strength to the input signal or the intermediate signal. The comparator (126) is coupled to the offset unit (122) and generates an output signal by comparing the two comparable signals which is indicative of the phase of the input signal.

Abstract: A sensor (10) has an output coupled to a first comparator input. A control circuit (18) is arranged to switch from an upward tracking mode to a downward relative level detection mode, to a downward tracking mode, to an upward relative level detection mode and back to the upward tracking mode successively. A first and second digital to analog conversion circuit (14a,b) receive a first and second digital control value from the control circuit (18) respectively.