Abstract: A fully digital phase-locked loop comprises a sampler (1), an analog-to-digital converter (2), two quadrature demodulators (3 and 4) and their associated filters (5 and 6), and a decision logic (7) effecting the correction of the sampling phase around the value of the free-running frequency (f.sub.e) by the addition or subtraction of machine cycles of a signal processor (9).

Abstract: An analogue scrambling system with dynamic band permutation in which the speech signal is filtered (1), sampled (2) at the rate f.sub.e, digitized (3), transformed by means of an analysis filter bank (4) into N sub-band signals sampled at f.sub.e /N and transferred in a permuted order to a synthesis filter bank (13) accomplishing the calculations of the scrambled signal sampled at the rate f.sub.e. A set of permutations is protected in a memory (8) and a scrambling with dynamic permutation in time is obtained by changing the read addresses of the memory. The scrambled signal reconverted into an analogue signal (14, 15) is transmitted through an analogue channel to an unscrambler where it is preprocessed so that the synchronizing and equalizing functions are accomplished and where the accomplished processes are identical with those accomplished in the scrambler, the difference being that the permuted order of the N sub-band signals is restored.

Abstract: This device for summing squares is designed to calculate the sum of the squares of "n" numbers with "m" binary elements, where n and m are whole numbers equal to or greater than "2"; it is made up from a systolic network 14 formed of identical cells arranged in lines and columns and around which is arranged a first peripheral circuit 16 to supply signals to the upper line, a second peripheral circuit 18 to supply signals to the input column also receiving signals from a presentation circuit 20 acting as an interface between the "n" numbers and the systolic network and finally an output circuit 22 connected to the lower line. Each line of the network is allocated to the calculation of the square of each of the numbers. Calculations are carried forward from the upper to the lower line via links between the lines. The output circuit consists of an adder component supplying the result from the calculations brought forward from the last line.

Abstract: In a signal analysing and synthesizing filter bank system, the analysing bank receives a signal sampled at the rate f.sub.e and produces N contiguous subbank signals sampled at the rate f.sub.e /N. From the subband signals the synthesizing bank must recover the incoming signal. These filter banks are formed by modulation of a prototype filter by sinusoidal signals which, for subband k (O.ltoreq.k.ltoreq.N=1), have a frequency (2k30 1)f.sub.e /(4N) and respective phases +(2k+1).pi./4 and -(2k+1).pi./4 for the analysing and synthesizing banks. These signals are furthermore delayed by a time delay (N.sub.c -1)/2f.sub.e), where N.sub.c is the number of coefficients of the prototype filter.