Patents by Inventor Jae-Goo Lee

Jae-Goo Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170137295
    Abstract: A method of preparing silicon using silica includes placing silica in a reaction chamber; adding a reducing agent into the reaction chamber; feeding a material for impact into the reaction chamber and sealing the reaction chamber; and reducing the silica to silicon by allowing the material for impact to generate a physical impact inside the reaction chamber. The preparation method of silicon using silica does not employ a high-temperature high-pressure process and provides a preparation method of silicon by which the porous structure of the silica before a reduction reaction is maintained within the silicon even after the reaction.
    Type: Application
    Filed: July 1, 2016
    Publication date: May 18, 2017
    Inventors: Won Chul CHO, Myung Won SEO, Hai In LEE, Jae Goo LEE, Ho Won RA, Sang Jun YOON, Tae Young MUN
  • Patent number: 9646984
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 9, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Won Kim, Chang-Seok Kang, Young-Woo Park, Jae-Goo Lee, Jae-Duk Lee
  • Patent number: 9634024
    Abstract: A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: April 25, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kohji Kanamori, Chung-Jin Kim, Young-Woo Park, Jae-Goo Lee, Jae-Duk Lee, Moo-Rym Choi
  • Patent number: 9620511
    Abstract: A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: April 11, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-goo Lee, Young-woo Park, Jin-taek Park
  • Publication number: 20170092651
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 30, 2017
    Inventors: Jong-Won KIM, Chang-Seok KANG, Young-Woo PARK, Jae-Goo LEE, Jae-Duk LEE
  • Patent number: 9485081
    Abstract: An apparatus for compensating for a skew is provided between data signals supplied through a plurality of data lines and a clock signal supplied through a clock line. A skew compensation apparatus includes a plurality of data receivers each configured to delay a data signal supplied through a corresponding data line based on associated phase difference data and to output the delayed data signal, a clock receiver configured to receive a clock signal supplied through a clock line, and a phase controller configured to select any one of the plurality of data receivers and to output, to the selected data receiver, a phase control signal configured to correct the phase difference data of the selected data receiver based on the phase difference between a data signal output from the selected data receiver and the clock signal.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: November 1, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hee-Sun Ahn, Jae-Goo Lee, Choong-Sun Shin, Young-Uk Won, In-Bok Song
  • Publication number: 20160312697
    Abstract: The present invention relates to a gasification combined generation system including: a slurry mixer adapted to receive the coal and industrial waste water thereto and mix them to make a uniform-quality slurry; a slurry storage adapted to receive the uniform-quality slurry from the slurry mixer and store the slurry therein; a slurry pump adapted to convey the slurry from the slurry storage; a slurry gasifier adapted to gasify the slurry with at least one of oxygen and air as an oxidizer and produce gas and slag from the gasified slurry; a gas analyzer adapted to analyze the components of the gas discharged from the slurry gasifier; a gas purifier adapted to purify the discharged gas; a generator adapted to utilize the purified gas as a fuel to generate electricity; and a slag discharger adapted to discharge the slag therefrom.
    Type: Application
    Filed: July 31, 2015
    Publication date: October 27, 2016
    Applicant: Korea Institute of Energy Research
    Inventors: Sang-Jun Yoon, Ho-won Ra, Jae-goo Lee, Myung-won Seo, Sang-goo Jeon, Deog-keun Kim
  • Patent number: 9478768
    Abstract: In an aspect, an organic light-emitting display apparatus including: a substrate; at least one color filter formed on the substrate; an overcoat layer covering the at least one color filter; a first passivation layer formed on the overcoat layer; a light scattering layer formed on the first passivation layer; a first electrode formed on the light scattering layer; a second electrode facing the first electrode; and an organic layer located between the first and second electrodes is provided.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: October 25, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Min-Woo Lee, Young-Mo Koo, Jae-Goo Lee, Woo-Sik Jeon
  • Patent number: 9444072
    Abstract: In an aspect, an organic light-emitting display apparatus including: a substrate; at least one color filter formed on the substrate; an overcoat layer covering the at least one color filter; a first passivation layer formed on the overcoat layer; a light scattering layer formed on the first passivation layer; a first electrode formed on the light scattering layer; a second electrode facing the first electrode; and an organic layer located between the first and second electrodes is provided.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: September 13, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Min-Woo Lee, Young-Mo Koo, Jae-Goo Lee, Woo-Sik Jeon
  • Patent number: 9385170
    Abstract: A thin film transistor array panel according to an exemplary embodiment includes: a substrate; a thin film transistor positioned on the substrate; a first electrode connected to the thin film transistor; and a diffractive layer positioned between the substrate and the thin film transistor. The diffractive layer is positioned within a boundary line of semiconductors of the thin film transistor.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: July 5, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Woo-Sik Jeon, Young-Mo Koo, Min-Woo Lee, Jae-Goo Lee
  • Publication number: 20160104859
    Abstract: An organic light emitting diode display includes a transistor, a first electrode connected to the transistor, a pixel definition layer on the first electrode, and an organic emission layer on the first electrode and corresponding to the emission region. The pixel definition layer exposes an emission region corresponding to a portion of the first electrode. The display also includes an auxiliary conductive pattern, a buffer layer, and a second electrode. The auxiliary conductive pattern does not overlap the emission region and is on the pixel definition layer. The buffer layer covers the organic emission layer and the pixel definition layer and contacts the auxiliary conductive pattern. The second electrode is on the buffer layer.
    Type: Application
    Filed: May 27, 2015
    Publication date: April 14, 2016
    Inventors: Se IL KIM, Young Shin LEE, Jae Goo LEE
  • Publication number: 20160093637
    Abstract: A method of fabricating a memory device includes alternately stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate, forming a channel hole by etching the insulating layers and the sacrificial layers to expose a partial region of the substrate, forming a channel structure in the channel hole, forming an opening by etching the insulating layers and the sacrificial layers to exposed a portion of the substrate, forming a plurality of side openings that include first side openings and a second side opening by removing the sacrificial layers through the opening, forming gate electrodes to fill the first side openings, and forming a blocking layer to fill the second side opening.
    Type: Application
    Filed: August 21, 2015
    Publication date: March 31, 2016
    Inventors: Jae-goo LEE, Young-woo PARK
  • Patent number: 9293172
    Abstract: A vertical type semiconductor device includes a pillar structure protruding from a top surface of a substrate of a cell array region. Word lines extend while surrounding the pillar structure. Word line contacts contact edges of the word lines functioning as pad portions. An insulating interlayer pattern is provided on the substrate of a peripheral circuit region, which is disposed at an outer peripheral portion of the cell array region. A first contact plug contacts the substrate of the peripheral circuit region. A second contact plug contacts a top surface of the first contact plug and has a top surface aligned on the same plane with the top surfaces of the word line contacts. The first and second contact plugs are stacked in the peripheral circuit region, so the failure of the vertical type semiconductor device is reduced.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Goo Lee, Jin-Soo Lim
  • Publication number: 20150380431
    Abstract: A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.
    Type: Application
    Filed: March 9, 2015
    Publication date: December 31, 2015
    Inventors: KOHJI KANAMORI, CHUNG-JIN KIM, YOUNG-WOO PARK, JAE-GOO LEE, JAE-DUK LEE, MOO-RYM CHOI
  • Publication number: 20150372101
    Abstract: A semiconductor device including a substrate, channels, a gate stack, and a pad separating region. The substrate has a pad region adjacent to a cell region. The channels extend in a direction crossing an upper surface of the substrate in the cell region. The gate stack includes a plurality of gate electrode layers spaced apart from each other on the substrate and enclosing the channels in the cell region. The pad separating region separates the gate stack into two or more regions in the pad region. The gate electrode layers have different lengths in the pad region.
    Type: Application
    Filed: March 19, 2015
    Publication date: December 24, 2015
    Inventors: Jae Goo LEE, Young Woo PARK
  • Patent number: 9175224
    Abstract: A gasifying apparatus including a variable gasifier and used as both a power generator and a combustion boiler and a method of driving the same are disclosed. A combustion boiler and a generator engine, driven with synthesis gas, are associated with a single gasifier, and the gasifying apparatus produces synthesis gas proper to a technical field of the gasifier by selectively applying an upflow gasifier and a downflow gasifier according to the technical field of the gasifier.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: November 3, 2015
    Assignee: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Jae Goo Lee, Sang Jun Yoon, Yong Ku Kim, Jae Ho Kim
  • Patent number: 9093038
    Abstract: A voltage stabilizer circuit for alternately or simultaneously stabilizing first and second generated voltages includes shared capacitor connected between the first and second generated voltages. The voltage stabilizer circuit may further include first and second switches for alternately connecting the first and second electrode of the shared capacitor to a ground. The alternation of the stabilized first and second voltages output by the voltage stabilizer circuit can be synchronized with a pixel polarity inversion mode signal output by the internal driver circuit of an LCD display.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: July 28, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-hun Han, Jae-goo Lee
  • Patent number: 9090840
    Abstract: A hydrogen sulfide and carbonyl sulfide removal method using microwave plasma comprising a hydrogen sulfide and carbonyl sulfide containing mixed-gas supplying step, a microwave supplying step, a plasma flame forming step, a hydrogen sulfide and carbonyl sulfide decomposing step in which hydrogen sulfide and the carbonyl sulfide are dissociated into atomic units, a rebinding step in which atomic units are rebound so that combustible gases are generated, and a separately collecting step in which the gases are separated and then are separately collected.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: July 28, 2015
    Assignee: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Sang Jun Yoon, Jae Goo Lee, Yong Ku Kim
  • Patent number: 9076978
    Abstract: An organic light emitting diode device includes a first electrode and a second electrode facing each other, a charge-generating layer interposed between the first electrode and the second electrode, a first light emitting unit that emits blue and is interposed between the first electrode and the charge-generating layer, and a second light emitting unit that emits white by combining the blue and is interposed between the second electrode and the charge-generating layer. The first light emitting unit includes a blue emission layer, a first charge transport layer disposed on one side of the blue emission layer and including an alkali metal complex compound and a first charge transport material, and a second charge transport layer disposed on one side of the first charge transport layer and including the alkali metal complex compound and a second charge transport material that has different charge mobility from the first charge transport material.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: July 7, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Min-Woo Lee, Young-Mo Koo, Jae-Goo Lee, Woo-Sik Jeon
  • Publication number: 20150132906
    Abstract: A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.
    Type: Application
    Filed: January 19, 2015
    Publication date: May 14, 2015
    Inventors: Sung-Il Chang, Young Woo Park, Jae Goo Lee