Abstract: An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.

Abstract: An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.

Abstract: A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a finger of the multi-fingered device can be activated.

Abstract: A technique for setting Vgg in an IC is disclosed. The technique includes specifying a design reliability lifetime for the IC, and a relationship between maximum gate bias and gate dielectric thickness for the IC sufficient to achieve the design reliability lifetime is established. The IC is fabricated and the gate dielectric thickness is measured. A maximum gate bias voltage is determined according to the gate dielectric thickness and the relationship between maximum gate bias and gate dielectric thickness, and a Vgg trim circuit of the IC is set to provide Vgg having the maximum gate bias voltage that will achieve the design reliability lifetime according to the measured gate dielectric thickness.

Abstract: An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.

Abstract: In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a first conductivity type. A channel region is included within the active area. A gate region overlays the channel region, and the first source/drain region and the second source/drain region are embedded in the active area and spaced from each other by the channel region. The first source/drain region and the second source/drain region each include a second semiconductor material of a second conductivity type opposite of the first conductivity type. A well-tap region is embedded in the active area and spaced from the first source/drain region by the channel region and the second source/drain region. The well-tap region includes the second semiconductor material of the first conductivity type. The first source/drain region and the second source/drain region and the well-tap region are epitaxial deposits.

Abstract: A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a finger of the multi-fingered device can be activated.

Abstract: A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Abstract: A photomask and a method for forming a photomask are disclosed in which the photomask pattern is modified to bridge features that are likely to produce electrostatic discharge related defects. In one embodiment those adjacent features that are closely spaced together and have a high surface area differential, are bridged using a bridge that has a width less than the minimum optical resolution of the photolithography process.

Abstract: A rapid thermal nitridation (RTN) process produces a nitrogen concentration gradient in an oxynitride layer to compensate for transistor threshold voltage effects from a thickness gradient in the oxynitride layer. The nitrogen concentration gradient is selected to allow greater dopant penetration through thicker gate dielectrics in PMOS transistors formed using the oxynitride layer. Any increases in threshold voltage due to thicker gate dielectrics are counteracted by corresponding decreases in threshold voltage due to dopant penetration, allowing consistent threshold voltage values to be maintained for all PMOS transistors on a single wafer. The nitrogen concentration gradient can be introduced by regulating the flow of nitrous oxide during RTN processing to cause an accumulation of atomic oxygen to develop within the process chamber.

Abstract: A rapid thermal nitridation (RTN) process produces a nitrogen concentration gradient in an oxynitride layer to compensate for transistor threshold voltage effects from a thickness gradient in the oxynitride layer. The nitrogen concentration gradient is selected to allow greater dopant penetration through thicker gate dielectrics in PMOS transistors formed using the oxynitride layer. Any increases in threshold voltage due to thicker gate dielectrics are counteracted by corresponding decreases in threshold voltage due to dopant penetration, allowing consistent threshold voltage values to be maintained for all PMOS transistors on a single wafer. The nitrogen concentration gradient can be introduced by regulating the flow of nitrous oxide during RTN processing to cause an accumulation of atomic oxygen to develop within the process chamber.

Abstract: A rapid thermal nitridation (RTN) process produces a nitrogen concentration gradient in an oxynitride layer to compensate for transistor threshold voltage effects from a thickness gradient in the oxynitride layer. The nitrogen concentration gradient is selected to allow greater dopant penetration through thicker gate dielectrics in PMOS transistors formed using the oxynitride layer. Any increases in threshold voltage due to thicker gate dielectrics are counteracted by corresponding decreases in threshold voltage due to dopant penetration, allowing consistent threshold voltage values to be maintained for all PMOS transistors on a single wafer. The nitrogen concentration gradient can be introduced by regulating the flow of nitrous oxide during RTN processing to cause an accumulation of atomic oxygen to develop within the process chamber.

Abstract: A rapid thermal nitridation (RTN) process produces a nitrogen concentration gradient in an oxynitride layer to compensate for transistor threshold voltage effects from a thickness gradient in the oxynitride layer. The nitrogen concentration gradient is selected to allow greater dopant penetration through thicker gate dielectrics in PMOS transistors formed using the oxynitride layer. Any increases in threshold voltage due to thicker gate dielectrics are counteracted by corresponding decreases in threshold voltage due to dopant penetration, allowing consistent threshold voltage values to be maintained for all PMOS transistors on a single wafer. The nitrogen concentration gradient can be introduced by regulating the flow of nitrous oxide during RTN processing to cause an accumulation of atomic oxygen to develop within the process chamber.

Abstract: A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

Abstract: A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

Abstract: A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

Abstract: A method for forming a localized halo implant region, comprises: implanting a first dosage of ions of a first type toward a surface of a substrate having a gate electrode formed thereon, so as to form a lightly doped region adjacent to the gate electrode; forming a disposable spacer on a sidewall of the gate electrode; forming an elevated source/drain structure adjacent to the disposable spacer; implanting a second dosage of ions of the first type toward the surface of the substrate so as to form a heavily doped region adjacent to the disposable spacer; removing the disposable spacer; and tilt-angle implanting at least one dosage of ions of a second type toward a gap created by the disposable spacer having been removed so as to form a localized halo implant region in the substrate, preferably by utilizing shadow effects of the gate electrode and the elevated source/drain structure.

Abstract: A device isolation structure and a method thereof including a semiconductor substrate wherein a field isolation region including a plurality of dummy active regions and an active region are defined, a plurality of trenches formed among the regions, a filling layer filled in the plurality of trenches, a gate insulation layer formed on the semiconductor substrate having the filling layer, and a second conduction layer formed on the gate insulation layer, is capable of preventing a dishing from being generated in etching by forming the plurality of dummy active regions in the field isolation region and basically preventing the wide trenches from being formed, minimizing a parasitic capacitance generated in the dummy active-gate insulation layer-gate insulation layer in the field isolation region, and simplifying an isolation process by using the dummy active pattern.