Patents by Inventor Jae-hyoung Choi

Jae-hyoung Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090130457
    Abstract: A dielectric structure includes a first dielectric layer, a buffer oxide layer and a second dielectric layer. The lower dielectric layer has a material having a perovskite structure including titanium and is formed on a substrate. The buffer oxide layer is formed on the first dielectric layer. The second dielectric layer has a perovskite structure including titanium and is formed on the buffer oxide layer.
    Type: Application
    Filed: November 18, 2008
    Publication date: May 21, 2009
    Inventors: Wan-Don Kim, Jae-Hyoung Choi, Kyu-Ho Cho, Jung-Hee Chung, Jin-Yong Kim, Yong-Suk Tak
  • Patent number: 7495292
    Abstract: Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: February 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Hoon Oh, Jung-Hee Chung, Jae-Hyoung Choi, Jeong-Sik Choi, Sung-Tae Kim, Cha-Young Yoo
  • Patent number: 7482677
    Abstract: In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric layer pattern including a metal silicon oxynitride are formed, a control gate is formed on the dielectric structure. Since the dielectric structure includes at least one metal silicon oxide layer and at least one metal silicon oxynitride layer, the dielectric structure may have a high dielectric constant and a good thermal resistance. A non-volatile semiconductor memory device including the dielectric structure may have good electrical characteristics such as a large capacitance and a low leakage current.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: January 27, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Cheol Lee, Sung-Tae Kim, Young-Sun Kim, Cha-Young Yoo, Gab-Jin Nam, Young-Geun Park, Jae-Hyoung Choi, Jae-Hyun Yeo, Ha-Jin Lim, Yun-Seok Kim
  • Patent number: 7482242
    Abstract: Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. In a method of forming a capacitor, a lower electrode may be formed on a substrate, and then a dielectric layer may be formed on the lower electrode. An upper electrode structure may be formed on the dielectric layer. The upper electrode structure may include a first upper electrode and a second upper electrode. The second upper electrode may include at least two of a silicon layer, a first silicon germanium layer and a second silicon germanium layer doped with p-type impurities.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: January 27, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Bum Park, Woo-Sung Lee, Nam-Kyu Kim, Jung-Hee Chung, Jae-Hyoung Choi
  • Patent number: 7442981
    Abstract: Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: October 28, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gab-Jin Nam, Young-Sun Kim, Cha-Young Yoo, Jong-Cheol Lee, Jin-Tae Noh, Jae-Young Ahn, Young-Geun Park, Jae-Hyoung Choi, Jae-Hyun Yeo
  • Patent number: 7442604
    Abstract: Provided are methods of manufacturing dielectric films including forming a first dielectric film on a wafer using atomic layer deposition (ALD) in a first batch type apparatus, forming a second dielectric film on the first dielectric film using atomic layer deposition in a second batch type apparatus, wherein the second dielectric film has a higher crystallization temperature than the first dielectric film and forming a third dielectric film on the second dielectric film using atomic layer deposition in a third batch type apparatus. Methods of manufacturing metal-insulator-metal (MIM) capacitors using the methods of forming the dielectric films and batch type atomic layer deposition apparatus for forming the dielectric films are also provided.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: October 28, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyoung Choi, Jung-hee Chung, Se-hoon Oh, Jong-cheol Lee
  • Patent number: 7425761
    Abstract: A method of manufacturing a dielectric layer for a capacitor including sequentially supplying and purging a first and a second precursor material for a first and a second predetermined amount of time, respectively, in an initial cycle, sequentially supplying and purging the first and the second precursor materials for a third predetermined amount of time, which is shorter than the first and/or second predetermined amount of time, in a post cycle, which follows the initial cycle, and repeating the initial and post cycles to form a dielectric layer having a predetermined thickness.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: September 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Sung-ho Kang, Jung-hee Chung, Seog-min Lee, Jong-bom Seo, Young-min Kim
  • Patent number: 7422943
    Abstract: Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: September 9, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-cheol Lee, Young-sun Kim, Jung-hee Chung, Jae-hyoung Choi, Se-hoon Oh, Hong-bum Park
  • Patent number: 7416904
    Abstract: A fabrication method for forming a semiconductor device having a capacitor is provided. A capacitor dielectric layer is formed by depositing a first layer and a second layer. The second layer is a major portion of the capacitor dielectric layer. The first layer acts as a seed layer, while the second layer is expitaxially grown. The material of the second layer as deposited is partially crystal. Nuclear generation and crystal growth occur separately so that the crystalline characteristic of the capacitor dielectric layer and the capacitance characteristic of the capacitor are enhanced. Moreover, the capacitor dielectric layer is crystallized at a relatively low temperature or for a relatively short time, thereby reducing leakage current as well as reducing deformation in the lower electrode. Optionally, The material of the second layer as deposited is not partially crystal but amorphous.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 26, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyoung Choi, Cha-Young Yoo, Suk-Jin Chung, Wan-Don Kim
  • Patent number: 7338863
    Abstract: Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III transition metals may be formed on the floating gate using a pulsed laser deposition process. The dielectric layer pattern having an increased dielectric constant may be formed of metal oxide doped with a transition metal such as scandium, yttrium, or lanthanum.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: March 4, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Cheol Lee, Jae-Hyoung Choi, Han-Mei Choi, Gab-Jin Nam, Young-Sun Kim
  • Patent number: 7335550
    Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: February 26, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Wan-don Kim, Cha-young Yoo, Suk-jin Chung
  • Patent number: 7314806
    Abstract: A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a metal-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: January 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Sung-tae Kim, Ki-chul Kim, Cha-young Yoo, Jeong-hee Chung, Se-hoon Oh, Jeong-sik Choi
  • Patent number: 7304367
    Abstract: A MIM capacitor can include a doped polysilicon contact plug in an interlayer insulating film. A lower electrode of the MIM capacitor includes a transition metal nitride film is on the doped polysilicon contact plug. A transition metal silicide film is between the doped polysilicon contact plug and the transition metal nitride film.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: December 4, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Jung-hee Chung, Cha-young Yoo, Nam-myun Cho, Jeong-sik Choi, Se-hoon Oh, Dong-kyun Park
  • Publication number: 20070236863
    Abstract: A capacitor may have a pre-treatment layer formed on a lower electrode, reaction to a dielectric layer and/or deterioration of capacitor characteristics may be suppressed. At least part of the dielectric layer may be oxidized or nitridized after being oxidized, and increases in leakage current may be suppressed. In a method of fabricating a capacitor, a plasma treatment performed before and after the forming of the dielectric layer within the batch-type equipment may cause retention time between the plasma treatment and the deposition of the dielectric layer to be the same or substantially the same for each wafer and/or capacitors may show smaller variations in layer characteristics between wafers.
    Type: Application
    Filed: July 14, 2006
    Publication date: October 11, 2007
    Inventors: Jong-cheol Lee, Young-sun Kim, Jung-hee Chung, Kyoung-ryul Yoon, Ki-vin Im, Jae-hyoung Choi
  • Publication number: 20070145485
    Abstract: Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.
    Type: Application
    Filed: March 2, 2007
    Publication date: June 28, 2007
    Inventors: Se-Hoon Oh, Jung-Hee Chung, Jae-Hyoung Choi, Jeong-Sik Choi, Sung-Tae Kim, Cha-Young Yoo
  • Publication number: 20070099379
    Abstract: A method of manufacturing a dielectric layer for a capacitor including sequentially supplying and purging a first and a second precursor material for a first and a second predetermined amount of time, respectively, in an initial cycle, sequentially supplying and purging the first and the second precursor materials for a third predetermined amount of time, which is shorter than the first and/or second predetermined amount of time, in a post cycle, which follows the initial cycle, and repeating the initial and post cycles to form a dielectric layer having a predetermined thickness.
    Type: Application
    Filed: October 10, 2006
    Publication date: May 3, 2007
    Inventors: Jae-hyoung Choi, Sung-ho Kang, Jung-hee Chung, Seog-min Lee, Jong-bom Seo, Young-min Kim
  • Publication number: 20070099419
    Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.
    Type: Application
    Filed: December 19, 2006
    Publication date: May 3, 2007
    Inventors: Jae-hyoung Choi, Wan-don Kim, Cha-young Yoo, Suk-jin Chung
  • Patent number: 7205219
    Abstract: Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: April 17, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Hoon Oh, Jung-Hee Chung, Jae-Hyoung Choi, Jeong-Sik Choi, Sung-Tae Kim, Cha-Young Yoo
  • Publication number: 20070066015
    Abstract: Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. In a method of forming a capacitor, a lower electrode may be formed on a substrate, and then a dielectric layer may be formed on the lower electrode. An upper electrode structure may be formed on the dielectric layer. The upper electrode structure may include a first upper electrode and a second upper electrode. The second upper electrode may include at least two of a silicon layer, a first silicon germanium layer and a second silicon germanium layer doped with p-type impurities.
    Type: Application
    Filed: September 20, 2006
    Publication date: March 22, 2007
    Inventors: Hong-Bum Park, Woo-Sung Lee, Nam-Kyu Kim, Jung-Hee Chung, Jae-Hyoung Choi
  • Publication number: 20070040203
    Abstract: Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.
    Type: Application
    Filed: March 22, 2006
    Publication date: February 22, 2007
    Inventors: Jong-cheol Lee, Young-sun Kim, Jung-hee Chung, Jae-hyoung Choi, Se-hoon Oh, Hong-bum Park