Patents by Inventor Jae Hyoung Youn

Jae Hyoung Youn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11062631
    Abstract: A display device includes: a display panel including signal lines in a display area and a peripheral area, the signal lines extending in a column direction and spaced apart; and test lines electrically connected to the signal lines in the peripheral area, extending in the column direction and arranged to be spaced apart. The peripheral area includes: a first peripheral area; and a second peripheral area located between the display area and the first peripheral area. The test lines include: a first test line including: a 1-1 testing portion disposed on the first peripheral area; and a 1-2 testing portion disposed on the second peripheral area; and a second test line including: a 2-1 testing portion disposed on the second peripheral area. A width of the 1-1 testing portion of the first test line is larger than a width of the 1-2 testing portion of the first test line.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: July 13, 2021
    Inventors: Kwan Yup Shin, Jun Ho Bae, Jae Hyoung Youn, Da Young Lee
  • Patent number: 10950154
    Abstract: A display device including: a display panel including a plurality of pixels arranged therein; a plurality of gate lines disposed in the display panel to transfer gate signals to the pixels; and a gate driver disposed in the display panel to include a plurality of stages that generate gate signals and output them to the gate lines. A first one of the stages is connected with a first one and a second one of the gate lines through a gate pad, the gate pad includes a first gate pad, a second gate pad, and a third gate pad, and the first gate pad, the second gate pad, and the third gate pad are connected with each other through a gate pad connecting member.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwan-Yup Shin, Jun-Ho Bae, Jae Hyoung Youn, Da Young Lee, Jin Young Lee, Hyeok Jun Lee
  • Publication number: 20200312205
    Abstract: A display device includes: a display panel including signal lines in a display area and a peripheral area, the signal lines extending in a column direction and spaced apart; and test lines electrically connected to the signal lines in the peripheral area, extending in the column direction and arranged to be spaced apart. The peripheral area includes: a first peripheral area; and a second peripheral area located between the display area and the first peripheral area. The test lines include: a first test line including: a 1-1 testing portion disposed on the first peripheral area; and a 1-2 testing portion disposed on the second peripheral area; and a second test line including: a 2-1 testing portion disposed on the second peripheral area. A width of the 1-1 testing portion of the first test line is larger than a width of the 1-2 testing portion of the first test line.
    Type: Application
    Filed: December 31, 2019
    Publication date: October 1, 2020
    Inventors: Kwan Yup Shin, Jun Ho Bae, Jae Hyoung Youn, Da Young Lee
  • Publication number: 20200020263
    Abstract: A display device including: a display panel including a plurality of pixels arranged therein; a plurality of gate lines disposed in the display panel to transfer gate signals to the pixels; and a gate driver disposed in the display panel to include a plurality of stages that generate gate signals and output them to the gate lines. A first one of the stages is connected with a first one and a second one of the gate lines through a gate pad, the gate pad includes a first gate pad, a second gate pad, and a third gate pad, and the first gate pad, the second gate pad, and the third gate pad are connected with each other through a gate pad connecting member.
    Type: Application
    Filed: March 5, 2019
    Publication date: January 16, 2020
    Inventors: Kwan-Yup SHIN, Jun-Ho BAE, Jae Hyoung YOUN, Da Young LEE, Jin Young LEE, Hyeok Jun LEE
  • Patent number: 10162237
    Abstract: A display device includes a first substrate including a display area and a peripheral area disposed in a periphery of the display area. A gate line is disposed in the display area. A data line is insulated from the gate line and intersects the gate line. The data line includes a first portion and a second portion. The first portion is disposed in the display area, and the second portion is connected to the first portion and is disposed in the peripheral area. A thin-film transistor (TFT) is disposed in the display area of the first substrate and is connected to the gate and data lines. A first insulating pattern is disposed on the TFT. A second insulating pattern is disposed in the peripheral area and covers a part of the second portion of the data line. The second insulating pattern includes a same material as the first insulating pattern.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jee Hoon Han, Soo Chul Kim, Jae Yong Shin, Jae Hyoung Youn
  • Patent number: 9799678
    Abstract: A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byeong-Beom Kim, Je-Hyeong Park, Jae-Hyoung Youn, Jean-Ho Song, Jong-In Kim
  • Publication number: 20170077246
    Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
    Type: Application
    Filed: November 4, 2016
    Publication date: March 16, 2017
    Inventors: Pil-Sang YUN, Ki-Won KIM, Hye-Young RYU, Woo-Geun LEE, Seung-Ha CHOI, Jae-Hyoung YOUN, Kyoung-Jae CHUNG, Young-Wook LEE, Je-Hun LEE, Kap-Soo YOON, Do-Hyun KIM, Dong-Ju YANG, Young-Joo CHOI
  • Patent number: 9570477
    Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: February 14, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwang-Ho Lee, Jang-Soo Kim, Hong-Suk Yoo, Sang-Soo Kim, Shi-Yul Kim, Jae-Hyoung Youn
  • Publication number: 20170023839
    Abstract: A display device includes a first substrate including a display area and a peripheral area disposed in a periphery of the display area. A gate line is disposed in the display area. A data line is insulated from the gate line and intersects the gate line. The data line includes a first portion and a second portion. The first portion is disposed in the display area, and the second portion is connected to the first portion and is disposed in the peripheral area. A thin-film transistor (TFT) is disposed in the display area of the first substrate and is connected to the gate and data lines. A first insulating pattern is disposed on the TFT. A second insulating pattern is disposed in the peripheral area and covers a part of the second portion of the data line. The second insulating pattern includes a same material as the first insulating pattern.
    Type: Application
    Filed: February 10, 2016
    Publication date: January 26, 2017
    Inventors: JEE HOON HAN, Soo Chul Kim, Jae Yong Shin, Jae Hyoung Youn
  • Patent number: 9520412
    Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: December 13, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Pil-Sang Yun, Ki-Won Kim, Hye-Young Ryu, Woo-Geun Lee, Seung-Ha Choi, Jae-Hyoung Youn, Kyoung-Jae Chung, Young-Wook Lee, Je-Hun Lee, Kap-Soo Yoon, Do-Hyun Kim, Dong-Ju Yang, Young-Joo Choi
  • Patent number: 9443877
    Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: September 13, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Pil-Sang Yun, Ki-Won Kim, Hye-Young Ryu, Woo-Geun Lee, Seung-Ha Choi, Jae-Hyoung Youn, Kyoung-Jae Chung, Young-Wook Lee, Je-Hun Lee, Kap-Soo Yoon, Do-Hyun Kim, Dong-Ju Yang, Young-Joo Choi
  • Patent number: 9443881
    Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: September 13, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jean-Ho Song, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
  • Publication number: 20160204135
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate line disposed on a substrate and including a gate electrode; a gate insulating layer formed on the gate line; a first oxide semiconductor layer disposed on the gate insulating layer and formed of an oxide semiconductor; a data wiring layer disposed on the gate insulating layer and including data line intersecting with the gate line, a source electrode connected to the data line, and a drain electrode facing the drain electrode; and a second oxide semiconductor layer covering the source electrode and the drain electrode, wherein the data wiring layer includes copper or a copper alloy.
    Type: Application
    Filed: October 27, 2015
    Publication date: July 14, 2016
    Inventors: Hyung Min KIM, NAM JUNE KIM, Jae Hyoung YOUN, Jang Soo KIM, Se Myung KWON, Kang-Young LEE
  • Publication number: 20160181283
    Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.
    Type: Application
    Filed: February 11, 2016
    Publication date: June 23, 2016
    Inventors: Kwang-Ho LEE, Jang-Soo KIM, Hong-Suk YOO, Sang-Soo KIM, Shi-Yul KIM, Jae-Hyoung YOUN
  • Patent number: 9269729
    Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: February 23, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwang-Ho Lee, Jang-Soo Kim, Hong-Suk Yoo, Sang-Soo Kim, Shi-Yul Kim, Jae-Hyoung Youn
  • Publication number: 20150318317
    Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
    Type: Application
    Filed: July 13, 2015
    Publication date: November 5, 2015
    Inventors: Pil-Sang YUN, Ki-Won KIM, Hye-Young RYU, Woo-Geun LEE, Seung-Ha CHOI, Jae-Hyoung YOUN, Kyoung-Jae CHUNG, Young-Wook LEE, Je-Hun LEE, Kap-Soo YOON, Do-Hyun KIM, Dong-Ju YANG, Young-Joo CHOI
  • Publication number: 20150318312
    Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
    Type: Application
    Filed: July 14, 2015
    Publication date: November 5, 2015
    Inventors: Pil-Sang Yun, Ki-Won Kim, Hye-Young Ryu, Woo-Geun Lee, Seung-Ha Choi, Jae-Hyoung Youn, Kyoung-Jae Chung, Young-Wook Lee, Je-Hun Lee, Kap-Soo Yoon, Do-Hyun Kim, Dong-Ju Yang, Young-Joo Choi
  • Publication number: 20150270296
    Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.
    Type: Application
    Filed: June 1, 2015
    Publication date: September 24, 2015
    Inventors: Kwang-Ho LEE, Jang-Soo KIM, Hong-Suk YOO, Sang-Soo KIM, Shi-Yul KIM, Jae-Hyoung YOUN
  • Patent number: 9111805
    Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: August 18, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Pil-Sang Yun, Ki-Won Kim, Hye-Young Ryu, Woo-Geun Lee, Seung-Ha Choi, Jae-Hyoung Youn, Kyoung-Jae Chung, Young-Wook Lee, Je-Hun Lee, Kap-Soo Yoon, Do-Hyun Kim, Dong-Ju Yang, Young-Joo Choi
  • Patent number: 9046727
    Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: June 2, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwang-Ho Lee, Jang-Soo Kim, Hong-Suk Yoo, Sang-Soo Kim, Shi-Yul Kim, Jae-Hyoung Youn