Patents by Inventor Jae-Hyung Jang

Jae-Hyung Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210074772
    Abstract: Disclosed is a display device capable of being manufactured through a simplified process and having improved touch sensitivity. The display device includes an encapsulation unit disposed on a light-emitting element, a touch sensor disposed on the encapsulation unit, and an intermediate layer disposed between the encapsulation unit and the touch sensor. The intermediate layer includes a first intermediate layer, having a dielectric constant that is lower than a dielectric constant of an organic film disposed above or under the intermediate layer, and a second intermediate layer, having greater hardness than the first intermediate layer, whereby touch sensitivity is improved while processing is simplified.
    Type: Application
    Filed: November 18, 2020
    Publication date: March 11, 2021
    Inventors: Byong-Hoo KIM, Min-Joo KIM, Eun-Pyo HONG, Jae-Won LEE, Sang-Hoon PAK, Sang-Hyuk WON, Jae-Man JANG, Sung-Jin KIM, Jae-Hyung JANG
  • Publication number: 20210005653
    Abstract: A pixel of an image sensor is provided to include a control region and a detection region. The control region is configured to generate hole current in a substrate, and a detection region is configured to capture electrons generated by incident light and moved by the hole current. A depth of an outer detection region of the detection region is deeper than a depth of an inner detection region of the detection region.
    Type: Application
    Filed: October 10, 2019
    Publication date: January 7, 2021
    Inventor: Jae Hyung Jang
  • Patent number: 10886339
    Abstract: A display device prevents cracks from spreading to an active area. The display device includes a substrate including an active area and a non-active area having a bending area, a thin-film transistor disposed in the active area, a light-emitting element disposed in the active area and connected to the thin-film transistor, an encapsulation layer disposed on the light-emitting element, a touch sensor disposed on the encapsulation layer, a touch pad disposed in the non-active area, a first routing line connecting the touch sensor to the touch pad via a second routing line in the bending area, and a crack prevention layer disposed on the second routing line in the bending area. Thus, the crack prevention layer is capable of preventing the occurrence of cracks in the bending area BA, thus preventing cracks from spreading to the active area AA.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: January 5, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Sang-Hyuk Won, Min-Joo Kim, Jae-Won Lee, Sang-Hoon Pak, Byong-Hoo Kim, Ji-Hye Lee, Jae-Man Jang, Sung-Jin Kim, Jae-Hyung Jang
  • Patent number: 10872935
    Abstract: Disclosed is a display device capable of being manufactured through a simplified process and having improved touch sensitivity. The display device includes an encapsulation unit disposed on a light-emitting element, a touch sensor disposed on the encapsulation unit, and an intermediate layer disposed between the encapsulation unit and the touch sensor. The intermediate layer includes a first intermediate layer, having a dielectric constant that is lower than a dielectric constant of an organic film disposed above or under the intermediate layer, and a second intermediate layer, having greater hardness than the first intermediate layer, whereby touch sensitivity is improved while processing is simplified.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 22, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Byong-Hoo Kim, Min-Joo Kim, Eun-Pyo Hong, Jae-Won Lee, Sang-Hoon Pak, Sang-Hyuk Won, Jae-Man Jang, Sung-Jin Kim, Jae-Hyung Jang
  • Publication number: 20200313085
    Abstract: A nonvolatile memory device having multi-level resistance and capacitance values is provided. Such a nonvolatile memory device includes: a substrate; a first electrode that is provided on the substrate; a dielectric layer that is provided on the first electrode, has resistance and capacitance changed by a tunneling conduction phenomenon of charges according to an applied voltage, has rectifying characteristics, and includes a dielectric material; an active layer that is provided on the dielectric layer, has resistance and capacitance changed according to an applied voltage, and includes a graphene oxide complex; and a second electrode that is provided on the active layer. In addition, the nonvolatile memory device has multi-level resistance and capacitance values according to an applied voltage.
    Type: Application
    Filed: March 20, 2018
    Publication date: October 1, 2020
    Applicant: Gwangju Institute of Science and Technology
    Inventors: Jae Hyung JANG, Rani ANOOP, Se I OH
  • Patent number: 10777551
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 15, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
  • Patent number: 10741788
    Abstract: Disclosed is a display device having a reduced non-display area. The display device includes an organic cover layer disposed on an encapsulation unit, an inner dam disposed between a substrate hole and a plurality of light-emitting elements, and a blocking element disposed between the substrate hole and the inner dam, the blocking element being disposed under the organic cover layer, whereby it is possible to prevent damage to a light-emitting stack. In addition, since the substrate hole is disposed in an active area, it is possible to reduce the size of a non-display area.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: August 11, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sang-Hyuk Won, Min-Joo Kim, Jae-Won Lee, Sang-Hoon Pak, Jae-Hyung Jang, Yeon-Woo Shin, Ji-Hun Lee
  • Publication number: 20200251592
    Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.
    Type: Application
    Filed: April 17, 2020
    Publication date: August 6, 2020
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Jae Hyung JANG, Jin Yeong SON, Hee Hwan JI
  • Patent number: 10700667
    Abstract: Disclosed are a metal-semiconductor-metal two-dimensional electron gas varactor (MSM-2DEG) and a method of manufacturing the same. There is provided an MSM-2DEG varactor having an asymmetric structure, which includes a first gate formed on a semiconductor layer, and a second gate spaced apart at a predetermined distance from the first gate and formed on the semiconductor layer, wherein the first gate and the second gate are different in shape and gate length.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 30, 2020
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jae Hyung Jang, Ji Hyun Hwang
  • Patent number: 10700198
    Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 30, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Hyung Jang, Jin Yeong Son, Hee Hwan Ji
  • Publication number: 20200194714
    Abstract: Disclosed is a display device having a reduced non-display area. The display device includes an organic cover layer disposed on an encapsulation unit, an inner dam disposed between a substrate hole and a plurality of light-emitting elements, and a blocking element disposed between the substrate hole and the inner dam, the blocking element being disposed under the organic cover layer, whereby it is possible to prevent damage to a light-emitting stack. In addition, since the substrate hole is disposed in an active area, it is possible to reduce the size of a non-display area.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 18, 2020
    Inventors: Sang-Hyuk WON, Min-Joo KIM, Jae-Won LEE, Sang-Hoon PAK, Jae-Hyung JANG, Yeon-Woo SHIN, Ji-Hun LEE
  • Patent number: 10686071
    Abstract: A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain region.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 16, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Hyung Jang, Hee Hwan Ji, Jin Yeong Son
  • Publication number: 20200150847
    Abstract: The present disclosure relates to a display device for improving productivity. The display device having a touch sensor is configured such that the total thickness of at least one inorganic insulation layer disposed on the region above each of dams is different from the total thickness of the at least one inorganic insulation layer disposed on a trench region between the dams. Thus, a photoresist for forming a routing line is formed so as to have a uniform thickness on the region above each of the dams and the trench region between the dams, and thus productivity is improved.
    Type: Application
    Filed: October 25, 2019
    Publication date: May 14, 2020
    Inventors: Jae-Hyung JANG, Min-Joo KIM, Eun-Pyo HONG, Jae-Won LEE, Sang-Hoon PAK, Sang-Hyuk WON, Yeon-Woo SHIN, Ji-Hun LEE
  • Publication number: 20200152707
    Abstract: A display device prevents cracks from spreading to an active area. The display device includes a substrate including an active area and a non-active area having a bending area, a thin-film transistor disposed in the active area, a light-emitting element disposed in the active area and connected to the thin-film transistor, an encapsulation layer disposed on the light-emitting element, a touch sensor disposed on the encapsulation layer, a touch pad disposed in the non-active area, a first routing line connecting the touch sensor to the touch pad via a second routing line in the bending area, and a crack prevention layer disposed on the second routing line in the bending area. Thus, the crack prevention layer is capable of preventing the occurrence of cracks in the bending area BA, thus preventing cracks from spreading to the active area AA.
    Type: Application
    Filed: October 28, 2019
    Publication date: May 14, 2020
    Inventors: Sang-Hyuk WON, Min-Joo KIM, Jae-Won LEE, Sang-Hoon PAK, Byong-Hoo KIM, Ji-Hye LEE, Jae-Man JANG, Sung-Jin KIM, Jae-Hyung JANG
  • Publication number: 20200152708
    Abstract: Disclosed is a display device capable of being manufactured through a simplified process and having improved touch sensitivity. The display device includes an encapsulation unit disposed on a light-emitting element, a touch sensor disposed on the encapsulation unit, and an intermediate layer disposed between the encapsulation unit and the touch sensor. The intermediate layer includes a first intermediate layer, having a dielectric constant that is lower than a dielectric constant of an organic film disposed above or under the intermediate layer, and a second intermediate layer, having greater hardness than the first intermediate layer, whereby touch sensitivity is improved while processing is simplified.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 14, 2020
    Inventors: Byong-Hoo KIM, Min-Joo Kim, Eun-Pyo Hong, Jae-Won Lee, Sang-Hoon Pak, Sang-Hyuk Won, Jae-Man Jang, Sung-Jin Kim, Jae-Hyung Jang
  • Publication number: 20200118998
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae KIM, Kwang II KIM, Jun Hyun KIM, In Sik JUNG, Jae Hyung JANG, Jin Yeong SON
  • Patent number: 10573645
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: February 25, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
  • Patent number: 10403780
    Abstract: There is provided a photoconductive semiconductor switch device comprising: a semiconductor substrate configured to generate electrons and holes using incident light thereto; at least one pair of conductive layers disposed on the semiconductor substrate, wherein one pair of the conductive layers consists of first and second conductive layers spaced apart from each other, wherein each of the first and second conductive layers contains abundant electrical carriers to have a low resistance; and first and second electrodes disposed on at least partially on the first and second conductive layers respectively. In this way, the application of the photoconductive semiconductor switch device may be widened.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: September 3, 2019
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventor: Jae Hyung Jang
  • Patent number: 10270182
    Abstract: Provided is a metamaterial-based polarization converter in which a reception antenna and a transmission antenna are formed by using a metamaterial, to thus emit an incident non-polarized or polarized electromagnetic wave in an angle-converted polarization direction. The metamaterial-based electromagnetic wave polarization converter includes: a reception antenna made of a metamaterial and allowing incident electromagnetic waves to resonate at a surface of the reception antenna to generate a surface current; a transmission antenna at a rear side of the reception antenna, and made of an angle-converted metamaterial to thus allow the electromagnetic waves transferred from the reception antenna to resonate to then be emitted in a polarization direction; and a connector made of a conductive material that connects the reception antenna and the transmission antenna, to thereby transfer a surface current generated from the reception antenna to the transmission antenna.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 23, 2019
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jae Hyung Jang, Jeong min Woo
  • Publication number: 20190043986
    Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.
    Type: Application
    Filed: March 28, 2018
    Publication date: February 7, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Jae Hyung JANG, Jin Yeong SON, Hee Hwan JI