Patents by Inventor Jae Il Kim

Jae Il Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180124432
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 3, 2018
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREAN BROADCASTING SYSTEM
    Inventors: Mun Churl KIM, Bum Shik LEE, Jae Il KIM, Chang Seob PARK, Sang Jin HAHM, In Joon CHO, Keun Sik LEE, Byung Sun KIM
  • Publication number: 20180102150
    Abstract: A semiconductor device may include a valid command generation circuit and a training control circuit. The valid command generation circuit may be configured to latch an internal chip selection signal and an internal control signal in synchronization with a division clock signal to generate a latch chip selection signal and a latch control signal. The valid command generation circuit may be configured to generate a valid command for executing a predetermined function from the latch control signal. The training control circuit may be configured to generate a training result signal from the latch chip selection signal or the latch control signal based on a flag.
    Type: Application
    Filed: May 31, 2017
    Publication date: April 12, 2018
    Applicant: SK hynix Inc.
    Inventors: Geun Ho CHOI, Dong Kyun KIM, Jae Il KIM
  • Patent number: 9941020
    Abstract: A semiconductor device includes a plurality of first input pins; a parity check unit suitable for performing a parity check for command/address signals inputted to the plurality of first input pins, and determining the parity check result as a pass or fail; and one or more registers suitable for storing the inputted command/address signals when the parity check result is determined as the fail, wherein during a test operation, the number of signals having a first logic value among the command/address signals inputted to the plurality of first input pins does not correspond to the logic value of a parity bit.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 10, 2018
    Assignee: SK Hynix Inc.
    Inventors: Sang-Ah Hyun, Jae-Il Kim
  • Publication number: 20180090199
    Abstract: A refresh control device may include a first oscillator configured to generate a first oscillation signal, a second oscillator configured to generate a second oscillation signal having a different cycle from the first oscillation signal, a first address controller configured to latch an address in response to the first oscillation signal, and output the latched address when a refresh signal is enabled. The refresh control device may also include a second address controller configured to latch the address in response to the second oscillation signal, and output the latched address when the refresh signal is enabled. Further included may be a selector configured to select any one of the output of the first address controller and the output of the second address controller in response to a select signal, and output the selected output as a row hammer address.
    Type: Application
    Filed: April 25, 2017
    Publication date: March 29, 2018
    Applicant: SK hynix Inc.
    Inventors: Dae Suk KIM, Jae Il KIM
  • Patent number: 9928896
    Abstract: A refresh control device may include a first oscillator configured to generate a first oscillation signal, a second oscillator configured to generate a second oscillation signal having a different cycle from the first oscillation signal, a first address controller configured to latch an address in response to the first oscillation signal, and output the latched address when a refresh signal is enabled. The refresh control device may also include a second address controller configured to latch the address in response to the second oscillation signal, and output the latched address when the refresh signal is enabled. Further included may be a selector configured to select any one of the output of the first address controller and the output of the second address controller in response to a select signal, and output the selected output as a row hammer address.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 27, 2018
    Assignee: SK hynix Inc.
    Inventors: Dae Suk Kim, Jae Il Kim
  • Patent number: 9922728
    Abstract: A memory device may include a plurality of memory cells; and an error detection unit suitable for latching first read data of one or more memory cells selected from the plurality of memory cells after refreshing the selected memory cells, in a first phase, and suitable for detecting errors of the selected memory cells before refreshing the selected memory cells, in a second phase.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 20, 2018
    Assignee: SK Hynix Inc.
    Inventors: Min-Su Park, Jae-Il Kim
  • Patent number: 9911475
    Abstract: A semiconductor device includes an information signal conversion circuit suitable for generating a flag signal from an external control signal in response to an information signal, and an implicit precharge signal generation circuit suitable for generating an implicit precharge signal for performing a precharge operation between successive active operations, in response to the flag signal.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 6, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hun Kwon, Jae Il Kim
  • Publication number: 20180053567
    Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device outputs address signals. The first semiconductor device may receive or output data. The second semiconductor device may perform an impedance calibration operation and outputs pull-up codes and pull-down codes generated by the impedance calibration operation. The third semiconductor device may output internal data selected by the address signals as the data or store the data during a write operation or a read operation.
    Type: Application
    Filed: May 17, 2017
    Publication date: February 22, 2018
    Applicant: SK hynix Inc.
    Inventor: Jae Il KIM
  • Publication number: 20180040354
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to generate internal commands, internal addresses and internal data for performing an initialization operation. The second semiconductor device may be configured to store the internal data in a plurality of memory cells selected by the internal commands and the internal addresses.
    Type: Application
    Filed: June 16, 2017
    Publication date: February 8, 2018
    Applicant: SK hynix Inc.
    Inventors: Dae Suk KIM, Jae Il KIM, Hong Jung KIM
  • Publication number: 20180040355
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output commands and addresses. The first semiconductor device may be configured to output a strobe signal toggled and data after an initialization operation. The second semiconductor device may be configured to start the initialization operation if the commands have a first combination and stores internal data having a predetermined level during a set period of the initialization operation if the commands have a second combination.
    Type: Application
    Filed: June 16, 2017
    Publication date: February 8, 2018
    Applicant: SK hynix Inc.
    Inventors: Jae Il KIM, Hong Jung KIM, Dae Suk KIM
  • Publication number: 20180040363
    Abstract: A semiconductor device may be provided. The semiconductor device may include a power-down signal generation circuit and a refresh signal generation circuit. The power-down signal generation circuit may be configured to generate a power-down signal which is enabled during a power-down operation period based on a multi-operation signal that is generated by decoding commands. The refresh signal generation circuit may be configured to generate a refresh signal which is enabled during a refresh operation period based on the multi-operation signal and an operation selection signal.
    Type: Application
    Filed: June 14, 2017
    Publication date: February 8, 2018
    Applicant: SK hynix Inc.
    Inventors: Ki Hun KWON, Jae Il KIM
  • Patent number: 9888259
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: February 6, 2018
    Assignees: Korea Advanced Institute of Science and Technology, Korean Broadcasting System
    Inventors: Mun Churl Kim, Bum Shik Lee, Jae Il Kim, Chang Seob Park, Sang Jin Hahm, In Joon Cho, Keun Sik Lee, Byung Sun Kim
  • Patent number: 9875807
    Abstract: A semiconductor memory apparatus may include a data conversion control block configured to control the number of pipe input control signals and the number of pipe output control signals which are enabled, in response to a training control signal. The semiconductor memory apparatus may also include a data conversion block configured to receive parallel data and output serial data, in response to the pipe input control signals and the pipe output control signals.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: January 23, 2018
    Assignee: SK hynix Inc.
    Inventor: Jae Il Kim
  • Publication number: 20180002486
    Abstract: This invention relates to a polyamide-imide precursor, a polyamide-imide obtained by imidizing the same, a polyamide-imide film, and an image display device including the film. The polyamide-imide precursor includes, in a molecular structure thereof, a first block, obtained by copolymerizing monomers including dianhydride and diamine, and a second block, obtained by copolymerizing monomers including an aromatic dicarbonyl compound and aromatic diamine. The dianhydride includes biphenyltetracarboxylic acid dianhydride (BPDA) and 2-bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride (6FDA), and the diamine includes bistrifluoromethylbenzidine (TFDB).
    Type: Application
    Filed: December 30, 2015
    Publication date: January 4, 2018
    Applicant: KOLON INDUSTRIES, INC.
    Inventors: Jae Il KIM, Hak Gee JUNG
  • Patent number: 9859024
    Abstract: A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: January 2, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jong-Sam Kim, Jae-Il Kim
  • Publication number: 20170372760
    Abstract: A semiconductor device includes a first rank and a second rank. The first rank operates in synchronization with a clock signal in response to a first rank selection signal, and the second rank operates in synchronization with the clock signal in response to a second rank selection signal. The first rank performs a termination operation without performing an internal control operation if the first rank selection signal maintains an enabled state in synchronization with a first edge and a second edge of the clock signal.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 28, 2017
    Applicant: SK hynix Inc.
    Inventor: Jae Il KIM
  • Publication number: 20170365311
    Abstract: A semiconductor device may include a division control circuit and a latch circuit. The division control circuit may be configured to divide an external clock to generate a first preliminary divided clock and a second preliminary divided clock. The division control circuit may be configured to output the first and second preliminary divided clocks or any one of the first and second preliminary divided clocks as first and second divided clocks. The latch circuit may be configured to latch an external control signal in response to the first and second divided clocks and configured to output latched signals as first and second latch control signals.
    Type: Application
    Filed: June 5, 2017
    Publication date: December 21, 2017
    Applicant: SK hynix Inc.
    Inventor: Jae Il KIM
  • Publication number: 20170366169
    Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.
    Type: Application
    Filed: September 6, 2017
    Publication date: December 21, 2017
    Applicant: SK hynix Inc.
    Inventors: Seung Geun BAEK, Jae Il KIM
  • Publication number: 20170352400
    Abstract: A semiconductor memory device may include a row address generating circuit, a row active pulse generating circuit and a word line activating circuit. The row address generating circuit may generate a row address in response to a refresh command, a row active pulse, and a normal address. The row active pulse generating circuit may generate a row active pulse in response to a refresh signal and an active signal. The word line activating circuit may selectively enable a word line in response to the row address and the row active pulse.
    Type: Application
    Filed: April 11, 2017
    Publication date: December 7, 2017
    Applicant: SK hynix Inc.
    Inventor: Jae Il KIM
  • Patent number: 9838721
    Abstract: Disclosed are a method of encoding a division block in video encoding and a method of decoding a division block in video decoding. An input picture is divided into encoding unit blocks. The encoding unit blocks are divided into sub-blocks. The sub-blocks are encoded by selectively using at least one of intra prediction encoding and inter prediction encoding. A decoding process is performed through a reverse process of the encoding method. When pixel values of an encoding unit block are encoded in video encoding, the flexibility in selecting an encoding mode is increased and the efficiency of encoding is increased.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: December 5, 2017
    Assignees: Korea Advanced Institute of Science and Technology, Korean Broadcasting System
    Inventors: Mun Churl Kim, Bum Shik Lee, Jae Il Kim, Chang Seob Park, Sang Jin Hahm, In Joon Cho, Keun Sik Lee, Byung Sun Kim