Patents by Inventor Jae-Rok Kahng

Jae-Rok Kahng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220013581
    Abstract: A variable resistance memory device includes lower conductive lines extending in a first direction on a substrate and spaced apart from each other in a second direction crossing the first direction, peripheral transistors on the substrate and arranged under the lower conductive lines in a third direction crossing the first direction and the second direction, and lower contacts electrically connecting the lower conductive lines to the peripheral transistors and extending in the third direction. Each of the lower conductive lines includes a first lower extending portion extending in the first direction, a second lower extending portion offset in the second direction from the first lower extending portion and extending in the first direction, and a lower connecting portion connecting the first lower extending portion to the second lower extending portion. Each of the lower contacts is in the lower connecting portion of a respective one of the lower conductive lines.
    Type: Application
    Filed: June 28, 2021
    Publication date: January 13, 2022
    Inventors: Tae Hong Ha, Jae Rok Kahng
  • Patent number: 10559613
    Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, first and second recesses spaced apart from each other in a first direction within the substrate, a first gate electrode filling the first recess and protruding above the substrate, a second gate electrode filling the second recess and protruding above the substrate, a first source/drain formed between the first and second recesses, a second source/drain formed in an opposite direction to the first source/drain with respect to the first recess, and a third source/drain formed in an opposite direction to the first source/drain with respect to the second recess and electrically connected to the second source/drain.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung In Kim, Jae Kyu Lee, Jae Rok Kahng
  • Publication number: 20180182795
    Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, first and second recesses spaced apart from each other in a first direction within the substrate, a first gate electrode filling the first recess and protruding above the substrate, a second gate electrode filling the second recess and protruding above the substrate, a first source/drain formed between the first and second recesses, a second source/drain formed in an opposite direction to the first source/drain with respect to the first recess, and a third source/drain formed in an opposite direction to the first source/drain with respect to the second recess and electrically connected to the second source/drain.
    Type: Application
    Filed: November 15, 2017
    Publication date: June 28, 2018
    Inventors: SUNG IN KIM, Jae Kyu Lee, Jae Rok Kahng
  • Patent number: 9812539
    Abstract: Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench. The buried gate structure includes a gate insulation layer pattern, a gate electrode and a capping layer pattern. First and second impurity regions are provided at portions of the substrate adjacent to the buried gate structure, respectively. At least a portion of each of the first and second impurity regions face a sidewall of the buried gate structure. First and second buried contact structures are provided on the first and second impurity regions, respectively. Each of the first and second buried contact structures includes a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: November 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Jun Kim, Sung-In Kim, Jung-Woo Song, Jae-Rok Kahng, Dae-Won Kim
  • Publication number: 20160181385
    Abstract: Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench. The buried gate structure includes a gate insulation layer pattern, a gate electrode and a capping layer pattern. First and second impurity regions are provided at portions of the substrate adjacent to the buried gate structure, respectively. At least a portion of each of the first and second impurity regions face a sidewall of the buried gate structure. First and second buried contact structures are provided on the first and second impurity regions, respectively. Each of the first and second buried contact structures includes a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 23, 2016
    Inventors: Yong-Jun Kim, Sung-In KIM, Jung-Woo SONG, Jae-Rok KAHNG, Dae-Won KIM
  • Patent number: 8835252
    Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Seok Moon, Jae-Rok Kahng, Hyun-Seung Song, Dong-Soo Woo, Sang-Hyun Lee, Hyun-Jung Lee
  • Publication number: 20130344666
    Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.
    Type: Application
    Filed: May 24, 2013
    Publication date: December 26, 2013
    Inventors: Joon-Seok Moon, Jae-Rok Kahng, Hyun-Seung Song, Dong-Soo Woo, Sang-Hyun Lee, Hyun-Jung Lee
  • Patent number: 8497175
    Abstract: A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: July 30, 2013
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Jae-Rok Kahng, Makoto Yoshida, Se-Myeong Jang
  • Publication number: 20130043519
    Abstract: A device includes a semiconductor substrate and a gate insulation film lining a trench in an active region of the substrate. A gate electrode pattern is recessed in the trench on the gate insulation film and has an upper surface that has a nonuniform height. A dielectric pattern may be disposed on the gate electrode pattern in the trench.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 21, 2013
    Inventors: Joon-seok Moon, Jae-rok Kahng, Jin-woo Lee, Sung-sam Lee, Dong-soo Woo, Kyoung-ho Jung, Jung-kyu Jung
  • Patent number: 7952140
    Abstract: In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Myeong Jang, Makoto Yoshida, Jae-Rok Kahng, Hyun-Ju Sung, Hui-Jung Kim, Chang-Hoon Jeon
  • Patent number: 7879703
    Abstract: A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: February 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Ho Jung, Makoto Yoshida, Jae-Rok Kahng, Chul Lee, Joon-Seok Moon, Cheol-Kyu Lee, Sung-Il Cho
  • Publication number: 20100200933
    Abstract: A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.
    Type: Application
    Filed: April 23, 2010
    Publication date: August 12, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-Rok Kahng, Makoto Yoshida, Se-Myeong Jang
  • Publication number: 20100140692
    Abstract: In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.
    Type: Application
    Filed: February 12, 2010
    Publication date: June 10, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Myeong Jang, Makoto Yoshida, Jae-Rok Kahng, Hyun-Ju Sung, Hui-Jung Kim, Chang-Hoon Jeon
  • Patent number: 7728381
    Abstract: A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: June 1, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Rok Kahng, Makoto Yoshida, Se-Myeong Jang
  • Patent number: 7700445
    Abstract: For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Myeong Jang, Makoto Yoshida, Jae-Rok Kahng, Chul Lee, Keun-Nam Kim, Hyun-Ju Sung, Hui-Jung Kim, Kyoung-Ho Jung
  • Patent number: 7691689
    Abstract: In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: April 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Myeong Jang, Makoto Yoshida, Jae-Rok Kahng, Hyun-Ju Sung, Hui-Jung Kim, Chang-Hoon Jeon
  • Patent number: 7667266
    Abstract: A semiconductor device including an active pattern having a channel recess portion, and a method of fabricating the same, are disclosed. In one embodiment, the semiconductor device includes an active pattern including first active regions and a second active region interposed between the first active regions. The active pattern protrudes above a surface of a semiconductor substrate and includes a channel recess portion above the second active region and between the first active regions. A device isolation layer surrounds the active pattern and has a groove exposing side walls of the recessed second active region. A distance between opposing side walls of the first active regions exposed by the channel recess portion is greater than a distance between side walls of the groove. A gate pattern is located in the channel recess portion and extends along the groove.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: February 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Ho Jung, Makoto Yoshida, Jae-Rok Kahng, Chul Lee, Keun-Nam Kim
  • Publication number: 20090186471
    Abstract: A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.
    Type: Application
    Filed: January 20, 2009
    Publication date: July 23, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Ho Jung, Makoto Yoshida, Jae-Rok Kahng, Chul Lee, Joon-Seok Moon, Cheol-Kyu Lee, Sung-Il Cho
  • Publication number: 20080303085
    Abstract: A semiconductor device including an active pattern having a channel recess portion, and a method of fabricating the same, are disclosed. In one embodiment, the semiconductor device includes an active pattern including first active regions and a second active region interposed between the first active regions. The active pattern protrudes above a surface of a semiconductor substrate and includes a channel recess portion above the second active region and between the first active regions. A device isolation layer surrounds the active pattern and has a groove exposing side walls of the recessed second active region. A distance between opposing side walls of the first active regions exposed by the channel recess portion is greater than a distance between side walls of the groove. A gate pattern is located in the channel recess portion and extends along the groove.
    Type: Application
    Filed: May 7, 2008
    Publication date: December 11, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-Ho JUNG, Makoto YOSHIDA, Jae-Rok KAHNG, Chul LEE, Keun-Nam KIM
  • Publication number: 20070298599
    Abstract: For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.
    Type: Application
    Filed: May 21, 2007
    Publication date: December 27, 2007
    Inventors: Se-Myeong Jang, Makoto Yoshida, Jae-Rok Kahng, Chul Lee, Keun-Nam Kim, Hyun-Ju Sung, Hui-Jung Kim, Kyoung-Ho Jung