Abstract: The present disclosure relates to a DC-DC converter, a vehicle, and a control method including the same, and more particularly, to a DC-DC converter, a vehicle, and a control method including the same capable of effectively detecting and responding to an interlock failure of a connector.

Abstract: A method for controlling a vehicle includes determining the number of driving legs according to an output current target value of a DC-DC converter; selecting one or more legs to be switched as many as the number of the driving legs from among a plurality of legs included in the DC-DC converter based on accumulated operation time for each of the plurality of legs; and controlling an output current value of the DC-DC converter to follow the output current target value by switching the selected one or more legs.

Abstract: A vehicle is provided that includes a DC converter having a first end connected to a fuel cell, a second end connected to a high-voltage battery, and at least one switching element connected between the first end and the second end, a fuel cell control unit which controls an activation state of a running command for start of the fuel cell based on an on-off state of vehicle start, and a converter controller which controls a running state of the DC converter according to an initial start sequence, a shutdown sequence, or a restart sequence for the fuel cell based on the activation state of the running command.

Abstract: A direct current to direct current (DC-DC) converter, a vehicle including the converter, and a controlling method thereof are proposed. The DC-DC converter is capable of efficiently detecting and responding to miscoupling of a connector. The DC-DC converter includes a first inlet corresponding to a first DC terminal, a transformation circuit connected to the first DC terminal and a second DC terminal while being located therebetween, and a converter controller, wherein when receiving a voltage command corresponding to the first DC terminal from an external controller, the converter controller is configured to determine whether or not a connector coupled to the first inlet is miscoupled thereto based on whether or not a voltage of the first DC terminal follows the voltage command.

Abstract: A DC-DC converter, a vehicle including the converter, and a controlling method thereof are provided. The DC-DC converter includes a first capacitor connected to a first DC terminal, a second capacitor connected to a second DC terminal, a plurality of converting circuits each including at least an inductor and a plurality of switching elements, and connected to each other in parallel between the first capacitor and the second capacitor, and a controller configured to control an ON/OFF state of the plurality of switching elements provided of each of the converting circuits. When external power connection with respect to each of the first DC terminal and the second DC terminal is disconnected, the controller is configured to control states of the plurality of switching elements to sequentially provide a plurality of different discharge paths between opposite terminals of the second capacitor via the plurality of converting circuits.

Abstract: A DC-DC converter may include a first capacitor connected to a first DC end, a second capacitor connected to a second DC end, a power conversion circuit connected between the first capacitor and the second capacitor and including at least one switching element, and a controller determining, when the second capacitor is charged as the battery is connected to the second DC end, whether the at least one switching element has failed based on a first voltage that is a voltage between opposite ends of the first capacitor and a second voltage that is a voltage between opposite ends of the second capacitor.

Abstract: A label indicating exposure to water is disposed in a plastic member of the battery. The label is prevented from being separated and disappeared and from being exchanged or modified arbitrarily by a battery user by having an edge of the label molded to the battery case.

Abstract: A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

Abstract: An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

Abstract: A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

Abstract: An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

Abstract: An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

Abstract: A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

Abstract: Provided is a method of forming conductors (e.g., metal lines and/or bumps) for semiconductor devices and conductors formed from the same. First and second seed metal layers may be formed. At least one mask may be formed on a portion on which a conductor is to be formed. An exposed portion may be oxidized. The oxidized portion may be removed. A conductive structure may be formed on an upper surface of a portion which is not oxidized. The conductors may be metal lines and/or bumps. The conductive structures may be solder balls.

Abstract: Disclosed is a battery in which an A/S label is disposed in a plastic member of the battery and a method for manufacturing the same. According to the present invention, the A/S label is prevented from being separated and disappeared and from being exchanged or modified arbitrarily by a battery user.

Abstract: Disclosed are a method for manufacturing a battery in which an A/S label is disposed in a plastic member of the battery and a battery made by the method. In the battery made by the method according to the present invention, the A/S label is prevented from being separated and disappeared and from being exchanged or modified arbitrarily by a battery user.

Abstract: An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

Abstract: An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

Abstract: A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

Abstract: A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.