Abstract: A battery includes an electrode assembly including a first uncoated region and a second uncoated region; a battery housing accommodating the electrode assembly and electrically connected to the second uncoated region; a cap to cover an open portion on bottom of the battery housing; a first electrode terminal passing through a partially closed portion of the battery housing and being electrically isolated from the battery housing; and a first current collector coupled to the first uncoated region and connected to the first electrode terminal.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.

Abstract: Provided are an electrode assembly, a battery, and a battery pack and vehicle including the same. An electrode assembly, in which a first electrode, a second electrode, and a separator interposed therebetween are wound about an axis to define a core and an outer circumferential surface. At least one of the first electrode and the second electrode includes, at a long side end portion, an uncoated portion exposed beyond the separator in a direction of the axis. At least a part of the uncoated portion is bent in a radial direction of the electrode assembly to define a bent surface region having overlapping layers of the uncoated portion. The bent surface region includes a welding target region having a number of the overlapping layers of the uncoated portion, and the welding target region extends along a radial direction of the electrode assembly.

Abstract: A battery includes an electrode assembly including a first electrode, a second electrode and a separator between the first electrode and the second electrode wound around a winding axis to define a core and an outer circumferential surface, the first electrode including a first uncoated region in which an active material layer is not coated along a winding direction; a housing accommodating the electrode assembly through an open portion at a lower end thereof; a first current collector coupled to the first uncoated region and disposed in the housing; a cap to cover the open portion; and a spacer between the first current collector and the cap and having a height corresponding to a distance between the first current collector and the cap.

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: A camera module includes a housing, a movable body configured to move in a direction of an optical axis of the housing; a reinforcing member formed integrally on one surface of the movable body, and configured to increase a rigidity of the movable body; and a first buffer member formed in the reinforcing member, and configured to reduce an impactive force between the housing and the movable body.

Abstract: A semiconductor package including a die paddle, a first lead spaced apart from the die paddle and on one side of the die paddle, a second lead spaced apart from the die paddle and on another side of the die paddle, a spacer on the die paddle, a semiconductor die on the spacer, a first wire configured to connect an upper surface of the semiconductor die to the first lead, and a mold film configured to cover the die paddle, the first lead, the second lead, the spacer, the semiconductor die, and the first wire, wherein a first width of the spacer is greater than a second width of the die paddle so that the spacer overlaps the first lead may be provided.

Abstract: An image encoding/decoding method is provided. An image decoding method of the present invention may comprise deriving an intra-prediction mode of a current luma block, deriving an intra-prediction mode of a current chroma block based on the intra-prediction mode of the current luma block, generating a prediction block of the current chroma block based on the intra-prediction mode of the current chroma block, and the deriving of an intra-prediction mode of a current chroma block may comprise determining whether or not CCLM (Cross-Component Linear Mode) can be performed for the current chroma block.

Abstract: A display device including: a power supply configured to supply a first power, a second power, and a third power to a first power line, a second power line, and a third power line, respectively, wherein each of the first power, the second power and the third power varies in voltage level during one frame period; and pixels connected to at least one of scan lines and data lines, and connected to a common control line, the first power line, the second power line, and the third power line, wherein the pixels simultaneously emit light when the second power is changed to a low level, and a number of times the second power is changed to the low level during the one frame period changes in response to an image refresh rate.

Abstract: An apparatus for non-invasively measuring bio-information is provided. The apparatus for estimating bio-information may include a pulse wave sensor configured to measure a pulse wave signal from an object; a sensor position sensor configured to obtain sensor position information of the pulse wave sensor with respect to the object, based on the object being in contact with the pulse wave sensor; and a processor configured to estimate the bio-information based on blood vessel position information of the object, the sensor position information, and the pulse wave signal.

Abstract: The present invention relates to a technology for analyzing and detecting/diagnosing a target nucleic acid. When the detection system according to the present invention is used, effective real-time detection or diagnosis efficiency can be obtained while problems such as noise are minimized. In particular, since, by using a house-keeping gene according to a method of use, the expression difference of the target nucleic acid can be corrected, and direct real-time target nucleic acid detection is possible, it can be effectively used for detecting various nucleic acids and diagnosing various diseases thereby.

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract: Provided is a method for analyzing a reflection wave using effective impedance. The method includes the steps of: a) modeling a reflection surface of a building two-dimensionally; and b) obtaining a reflection wave by radiating a radio wave to the modeled reflection surface and analyzing the obtained reflection wave through making medium uniform.

Abstract: A program operation for a NOR flash memory device is verified by programming data in a memory cell, performing a dummy verify operation on the memory cell, and performing a program verify operation on the memory cell based on a result of the dummy verify operation.

Abstract: A NOR flash memory device includes a multi level memory cell coupled to a bit line configured to be sensed in response to a word line voltage, and a discharge circuit configured to discharge the bit line when the multi level memory cell is sensed as an on cell.