Abstract: An image processing device including: a gain value manager for generating white gain values corresponding to a plurality of positions, based on a sensing result of a predetermined white image; a target pixel manager for detecting saturated pixels, based on pixel values received from an external device, and determining target pixels as saturated white pixels of which each have a pixel value that indicates that the saturated white pixel is saturated, based on peripheral pixels of the saturated white pixels among the detected saturated pixels; and a target pixel corrector for changing pixel values of the target pixels, based on the white gain values and pixel values of the peripheral pixels.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: The present invention provides a pharmaceutical composition for prevention or treatment of a stress disease and depression, the pharmaceutical composition be safely useable without toxicity and side effects by using an extract of leaves of Vaccinium bracteatum Thunb., which is natural resource of Korea, so that the reduction of manufacturing and production costs and the import substitution and export effects can be expected through the replacement of a raw material for preparation with a plant inhabiting in nature.

Abstract: A monoclonal antibody or an antigen-binding fragment thereof according to an embodiment of the present invention can bind to lymphocyte-activation gene 3 (LAG-3) including a heavy chain variable region and a light chain variable region and inhibit the activity thereof. Thus it is expected to be useful for the development of immunotherapeutic agents for various disorders that are associated with LAG-3.

Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.

Abstract: A shoe management apparatus capable of managing various types of shoes and including a cabinet defining an inner space for storing shoes; and a partition dividing the inner space into an upper first compartment and a lower second compartment, formed therein with a fluid path along which air is discharged into the inner space, and variable in length with respect to a front-to-rear direction of the shoe management apparatus.

Abstract: Provided is a method of providing a user interface for video retrieval performed by a computing device, the method including: receiving a search query, providing a search result interface displaying at least one search video content and search section searched by the search query, wherein the search video content and the search section are related with at least one of a plurality of video semantic search attributes corresponding to the search query, and providing a timeline view interface for the search video content when it is determined to display the search result interface according to a timeline view mode, wherein the timeline view interface has a visual characteristic indicating the degree of relevance to at least one of the plurality of video semantic search attributes corresponding to the search query.

Abstract: A 1T DRAM cell device having two or more heterojunction surfaces perpendicular to the channel length direction and a quantum well at the drain region side. The 1T DRAM cell device described herein may be driven by GIDL or band-to-band tunneling, so that low voltage and high speed operation can be performed, and retention time and read current margin can be dramatically increased. It can also be driven as a memory device in harsh environments with high temperatures. Furthermore, since the heterojunction surfaces can be formed by vertically stacking epitaxial layers on a semiconductor substrate such as silicon, the conventional CMOS process technology can be used, and the area occupied by the device can be reduced as much as possible without limiting the channel length.

Abstract: An operating method of controller includes estimating, by a mean-bias manager, candidates of a mean bias voltage based on source read voltages corresponding to respective program states; determining, by a reliability interval manager, whether the candidates of the mean bias voltage are within confidence intervals respectively corresponding to the program states; selecting, by the reliability interval manager, the candidates of the mean bias voltage when the candidates of the mean bias voltage are within confidence intervals, respectively; deciding, by a read bias manager, target read voltages based on selected mean bias voltages or the selected candidates of the mean bias voltage; and reading, by a processor, target data according to the target read voltages.

Abstract: A memory controller for performing soft decoding according to a Cell Difference Probability (CDP) calculated based on a cell distribution controls a memory device. The memory controller for controlling the memory device, the memory controller comprising: an error corrector configured to correct an error in read data received from the memory device; a command generator configured to output, in response to failing an error correction operation of the error corrector, a cell distribution detection command for detecting threshold voltage distributions of memory cells included in the memory device; and a read voltage controller configured to determine, based on cell distribution detection data that the memory device provides in response to the cell distribution detection command, a number of read voltages for a read operation to be performed in the memory device and an interval between neighboring ones among the read voltages.

Abstract: A memory controller for performing soft decoding according to a Cell Difference Probability (CDP) calculated based on a cell distribution controls a memory device. The memory controller for controlling the memory device, the memory controller comprising: an error corrector configured to correct an error in read data received from the memory device; a command generator configured to output, in response to failing an error correction operation of the error corrector, a cell distribution detection command for detecting threshold voltage distributions of memory cells included in the memory device; and a read voltage controller configured to determine, based on cell distribution detection data that the memory device provides in response to the cell distribution detection command, a number of read voltages for a read operation to be performed in the memory device and an interval between neighboring ones among the read voltages.

Abstract: A controller for controlling a memory device includes a read control component suitable for controlling a recovery soft read operation of the memory device on bits contained in error correction-failed data groups, when error correction on data of a target data group and error correction on one or more of data of corresponding data groups failed; an error correction code (ECC) component suitable for performing the error correction, and performing a selective data recovery operation on the target data group depending on reliabilities of the respective bits, derived as a result of the recovery soft read operation; and a read bias determiner suitable for determining a recovery soft read voltage to maximize the number of bits recovered by the selective data recovery operation, among bits contained in the target data group.

Abstract: Designs of nonvolatile memory systems and memory operations that enable allocating reliability values associated with the hard data values from memory cells and performing an error correction operation for the hard data based on the reliability values. One example of a memory system includes a nonvolatile memory device including a plurality of memory cells, and a controller suitable for obtaining hard data by performing a hard read operation based on a hard read voltage for the memory cells, and performing an error correction operation for the hard data based on reliability values.

Abstract: A 1T DRAM cell device having two or more heterojunction surfaces perpendicular to the channel length direction and a quantum well at the drain region side. The 1T DRAM cell device described herein may be driven by GIDL or band-to-band tunneling, so that low voltage and high speed operation can be performed, and retention time and read current margin can be dramatically increased. It can also be driven as a memory device in harsh environments with high temperatures. Furthermore, since the heterojunction surfaces can be formed by vertically stacking epitaxial layers on a semiconductor substrate such as silicon, the conventional CMOS process technology can be used, and the area occupied by the device can be reduced as much as possible without limiting the channel length.

Abstract: An operating method of a memory system includes: reading a first data from a particular data group among a plurality of data groups included in a memory device; performing a first error correction code (ECC) decoding for the first data; when the first ECC decoding fails, reading a plurality of the remaining data other than the first data from the particular data group; performing a second ECC decoding for the plurality of the remaining data; when the second ECC decoding fails, identifying data, to which the second ECC decoding fails, among the plurality of the remaining data; obtaining first and second soft read values respectively corresponding to the first data, to which the first ECC decoding fails, and the second data, to which the second ECC decoding fails; determining reliability of the first and second data based on the first and second soft read values; and correcting the first data based on the reliability of the first and second data.

Abstract: A secured device including a security hardware module and a method thereof are provided. The secured device generates first user authentication information based on a user input, generates encryption key generation information corresponding to the first user authentication information, receives second user authentication information from an electronic device, and transmits to the electronic device the encryption key generation information corresponding to the first user authentication information when the second user authentication information matches the first user authentication information. The first user authentication information and the encryption key generation information are secured by the security hardware module.

Abstract: A controller for controlling a memory device includes a read control component suitable for controlling a recovery soft read operation of the memory device on bits contained in error correction-failed data groups, when error correction on data of a target data group and error correction on one or more of data of corresponding data groups failed; an error correction code (ECC) component suitable for performing the error correction, and performing a selective data recovery operation on the target data group depending on reliabilities of the respective bits, derived as a result of the recovery soft read operation; and a read bias determiner suitable for determining a recovery soft read voltage to maximize the number of bits recovered by the selective data recovery operation, among bits contained in the target data group.

Abstract: An operating method of controller includes estimating, by a mean-bias manager, candidates of a mean bias voltage based on source read voltages corresponding to respective program states; determining, by a reliability interval manager, whether the candidates of the mean bias voltage are within confidence intervals respectively corresponding to the program states; selecting, by the reliability interval manager, the candidates of the mean bias voltage when the candidates of the mean bias voltage are within confidence intervals, respectively; deciding, by a read bias manager, target read voltages based on selected mean bias voltages or the selected candidates of the mean bias voltage; and reading, by a processor, target data according to the target read voltages.

Abstract: This patent document provides designs of nonvolatile memory systems and memory operations that enable allocating reliability values associated with the hard data values from memory cells and performing an error correction operation for the hard data based on the reliability values. One example of a memory system includes a nonvolatile memory device including a plurality of memory cells, and a controller suitable for obtaining hard data by performing a hard read operation based on a hard read voltage for the memory cells, and performing an error correction operation for the hard data based on reliability values.

Abstract: An operation method of a data storage apparatus includes performing a first read operation using an optimal read voltage on read-failed memory cells, performing ECC decoding operation on read data, performing a second read operation using an oversampling read voltage on the read-failed memory cells when the ECC decoding operation fails, determining whether potential error memory cells which are turned on through the optimal read voltage and are turned off through the oversampling read voltage are present in the read data, determining whether neighboring memory cells which share a bit line with the potential error memory cells and are coupled to neighboring word lines are in erased state when the potential error memory cells are present, and inverting bit values corresponding to the potential error memory cells in the read data from the read-failed memory cells through the first read operation when neighboring memory cells are in erased state.