Patents by Inventor Jagdish Belani

Jagdish Belani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5650659
    Abstract: A semiconductor component package assembly including an integral radio frequency and electromagnetic interference shield is disclosed herein. The assembly includes a support member which supports an IC chip and defines an array of conductive leads. An electrically conductive shield is positioned relative to the IC chip so as to form an integral RF/EMI barrier between the IC chip and the ambient surroundings of the overall assembly. In a preferred embodiment, the shield is formed from different layers of material and configured for electrical connection of at least one conductive layer to certain ones of the leads which may include one or more ground leads.
    Type: Grant
    Filed: August 4, 1995
    Date of Patent: July 22, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Satya Chillara, Jagdish Belani
  • Patent number: 5046657
    Abstract: A tape automated bonding structure (10) includes a copper flexible tape (12) with a plurality of conductive leads (14) having tips (16) arranged in a generally rectangular pattern corresponding to gold bumped contacts (18) on semiconductor die (20). The tips (16) of the conductive leads (14) are configured as bumps extending from the remainder of each conductive lead (14). The tips (16) of the conductive leads (14) are gang bonded to the bumped contacts (18) on the semiconductor die (20) by positioning the tips (16) in registration over each bumped contact and applying heat and pressure to urge the tips (16) and the bumped contacts together, thus forming a thermocompression bond. The harder copper tips (16) penetrate into the gold bumped contacts. The bumped contacts (18) and the remainder of the tips (16) that has not penetrated into the contacts (18) space the conductive leads (14) above surface (22) of the semiconductor die (20).
    Type: Grant
    Filed: January 5, 1990
    Date of Patent: September 10, 1991
    Assignee: National Semiconductor Corporation
    Inventors: Venkat Iyer, Jagdish Belani, Hem P. Takiar, Rajenda Pendse
  • Patent number: 4876587
    Abstract: A one-piece interconnection structure (10) for an SO package (60) is formed from a single sheet strip (12) of copper having a thickness of about 8 mils. Contact finger patterns (14) are formed from a plurality of contact fingers (22) which extend in cantilever fashion. The fingers (22) have tips (24) of a reduced thickness of between about 2-3 mils. Stress relief slots (26) having a depth of about 2 mils are formed in the underside of each finger (22) spaced back from the tips (24) to give the fingers increased flexibility for downward bending during assembly operations. Vertical slots (28) on opposing sides of the fingers behind the stress relief slots give increased lateral flexibility to the fingers. Steps (30) extend vertically along the lateral fingers (22) and have two surfaces (32 and 34) angularly disposed with respect to central surface (36) on the top and bottom fingers.
    Type: Grant
    Filed: May 5, 1987
    Date of Patent: October 24, 1989
    Assignee: National Semiconductor Corporation
    Inventors: Robert Hilton, Ali Emamjomeh, Jagdish Belani
  • Patent number: 4595480
    Abstract: A system for electroplating metals, such as tin and solder on semiconductor lead frame strips includes a magazine for carrying the lead frames and a separate plating rack for carrying the magazines. The plating rack, which has an insulated surface, includes means for directing a current to the lead frame strips when the magazine is inserted in the plating rack. An electric coupling means is also provided for assuring that the current from the plating rack is evenly distributed among the individual lead frame strips so that uniform plating results. The magazine is suitable for transporting and storing the lead frame strips during assembly of semiconductor components, and it is unnecessary to remove the lead frame strips from the magazine for mounting on the plating rack.
    Type: Grant
    Filed: September 26, 1985
    Date of Patent: June 17, 1986
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Jagdish Belani