Patents by Inventor Jairus Legaspi Pisigan

Jairus Legaspi Pisigan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9034692
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; placing an integrated circuit device, having an external connector, adjacent to and electrically isolated from the lead; mounting an integrated circuit over the lead and the integrated circuit device with the integrated circuit electrically isolated from the integrated circuit device; and forming a package encapsulation, having an encapsulation base, over the lead, the integrated circuit, and the integrated circuit device with the lead and the external connector exposed from the encapsulation base.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: May 19, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan
  • Patent number: 8941219
    Abstract: An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: January 27, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jairus Legaspi Pisigan
  • Patent number: 8802555
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle and a lead adjacent to the die paddle; mounting an integrated circuit, having a bond pad, over the die paddle; forming a bonding interconnect on the bond pad; attaching a circuit end of an internal interconnect to the bonding interconnect, the bonding interconnect between the circuit end and the bond pad; and connecting a lead end of the internal interconnect to the lead.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: August 12, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Rachel Layda Abinan
  • Patent number: 8766428
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming external interconnects having bases of a first thickness and tips of a second thickness extending inwardly directly toward each other; connecting a first circuit device between the tips; attaching a second circuit device to the first circuit device with a combined thickness of the first circuit device and the second circuit device less than the first thickness; and forming an encapsulation of the first thickness between the bases and over the tips.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: July 1, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jairus Legaspi Pisigan
  • Patent number: 8652881
    Abstract: An integrated circuit package system includes: forming an anti-peel pad having both a concave ring and an external terminal with the concave ring, having a peripheral wall, surrounding the external terminal; connecting an integrated circuit with the anti-peel pad; and forming an encapsulation over the integrated circuit, the concave ring, and the external terminal with the encapsulation under the peripheral wall.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: February 18, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Henry Descalzo Bathan
  • Patent number: 8643157
    Abstract: An integrated circuit package system comprising: forming a paddle having a hole and an external interconnect; mounting an integrated circuit device having an active side to the paddle with the active side facing the paddle and the hole; connecting a first internal interconnect between the active side and the external interconnect through the hole; and encapsulating the integrated circuit device, the paddle, the first internal interconnect, and the external interconnect with the external interconnect partially exposed.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: February 4, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan
  • Patent number: 8637394
    Abstract: An integrated circuit package system includes: forming a flex bump over an integrated circuit device structure, the flex bump having both a base portion and an offset portion over the base portion; forming a first ball bond of a first internal interconnect over the offset portion; and encapsulating the integrated circuit device structure, the flex bump, and the first internal interconnect.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: January 28, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jairus Legaspi Pisigan, Henry Descalzo Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8558369
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a post of multiple plating layers having a base end with an inward protrusion, a connect riser, and a top end opposite the base end; positioning an integrated circuit device having a perimeter end facing the connect riser and the inward protrusion; attaching a bond wire directly on the inward protrusion and the integrated circuit device; and applying an encapsulation over the integrated circuit device, the bond wire, the inward protrusion, and around the post, the encapsulation exposing a portion of the base end and the top end of the post.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: October 15, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Frederick Rodriguez Gahilig, Jairus Legaspi Pisigan
  • Patent number: 8513801
    Abstract: An integrated circuit package system includes: mounting a first integrated circuit over a carrier; mounting an interposer, having an opening, over the first integrated circuit and the carrier with the interposer having an overhang over the carrier; connecting an internal interconnect, through the opening, between the carrier and the interposer; and forming an encapsulation over the first integrated circuit, the internal interconnect, and the carrier.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: August 20, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
  • Patent number: 8502371
    Abstract: An integrated circuit package system including: forming a die pad, wherein the die pad has a tiebar at a corner; forming a lead wherein the lead is connected to the tiebar; connecting an integrated circuit die to the die pad; and forming an encapsulation, having an edge, over the integrated circuit die with the lead extending from and beyond the edge.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 6, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Jairus Legaspi Pisigan, Henry Descalzo Bathan
  • Patent number: 8354742
    Abstract: A method of manufacturing a semiconductor package involves providing a substrate having a window. The substrate may include a leadframe having half-etched leads. First and second semiconductor devices are mounted to a top surface of the substrate on either side of the window using an adhesive. A third semiconductor device is mounted to the first and second semiconductor devices using an adhesive. The third semiconductor device is disposed over the window of the substrate. A wirebond or other electrical interconnect is formed between the third semiconductor device and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The wirebond or other electrical interconnect passes through the window of the substrate. An encapsulant is deposited over the first, second, and third semiconductor devices.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 15, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Jairus Legaspi Pisigan, Lionel Chien Hui Tay, Henry D. Bathan
  • Patent number: 8338233
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: December 25, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Henry Descalzo Bathan
  • Patent number: 8304337
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a device over a substrate including a bond wire pad row located between a perimeter of the substrate and the device; configuring the bond wire pad row to include three sided bond wire pads that horizontally overlap; and forming an interconnection between the device and the bond wire pad row.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
  • Patent number: 8304869
    Abstract: An integrated circuit package on package system includes: providing a lead having a wire-bonded die with a bond wire connected thereto; mounting a fan-in interposer over the wire-bonded die and the bond wire; connecting the fan-in interposer to the lead with the bond wires; and encapsulating the wire-bonded die, bond wires, and the fan-in interposer with an encapsulation leaving a portion of the fan-in interposer exposed.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Lionel Chien Hui Tay, Henry Descalzo Bathan
  • Patent number: 8278148
    Abstract: An integrated circuit package system is provided including forming a leadframe having a frame and a die paddle having leads thereon. The leads are held with respect to the die paddle. The leads are separated from the die paddle, and a die is attached to the die paddle. Bond wires are bonded between the leads and the die. The die and bond wires are encapsulated. The leadframe is singulated to separate the frame and the die paddle.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: October 2, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Jairus Legaspi Pisigan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho
  • Publication number: 20120241983
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; placing an integrated circuit device, having an external connector, adjacent to and electrically isolated from the lead; mounting an integrated circuit over the lead and the integrated circuit device with the integrated circuit electrically isolated from the integrated circuit device; and forming a package encapsulation, having an encapsulation base, over the lead, the integrated circuit, and the integrated circuit device with the lead and the external connector exposed from the encapsulation base.
    Type: Application
    Filed: March 21, 2011
    Publication date: September 27, 2012
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan
  • Publication number: 20120241931
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle and a lead adjacent to the die paddle; mounting an integrated circuit, having a bond pad, over the die paddle; forming a bonding interconnect on the bond pad; embedding a circuit end of an internal interconnect in the bonding interconnect; and connecting a lead end of the internal interconnect to the lead.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Rachel Layda Abinan
  • Publication number: 20120241968
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a post of multiple plating layers having a base end with an inward protrusion, a connect riser, and a top end opposite the base end; positioning an integrated circuit device having a perimeter end facing the connect riser and the inward protrusion; attaching a bond wire directly on the inward protrusion and the integrated circuit device; and applying an encapsulation over the integrated circuit device, the bond wire, the inward protrusion, and around the post, the encapsulation exposing a portion of the base end and the top end of the post.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 27, 2012
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Frederick Rodriguez Dahilig, Jairus Legaspi Pisigan
  • Patent number: 8258614
    Abstract: An integrated circuit package system comprising: providing a substrate having a cavity; sealing a package over the cavity of the substrate; and forming an encapsulant over the package and a portion of the substrate substantially preventing the encapsulant from forming in the cavity.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: September 4, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Abelardo Jr. Hadap Advincula, Lionel Chien Hui Tay
  • Patent number: 8236607
    Abstract: A method of manufacture an integrated circuit packaging system includes: providing a substrate; attaching a base component to the substrate by a first interconnect; attaching a stack component connected by a second interconnect to the substrate and partially over the base component, the second interconnect different from the first interconnect; molding an encapsulation over the base component, the first interconnect, the stack component, and the second interconnect; and removing the substrate to partially expose the first interconnect and the second interconnect from the encapsulation.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: August 7, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan