Patents by Inventor Jakub T. Kedzierski
Jakub T. Kedzierski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230396188Abstract: An actuator with a stack of thin layers operates by electrowetting droplets between the layers. The actuator includes a first layer structure and a second layer structure positioned adjacent to the first layer structure. One or more liquid droplets are pinned to one of the layers and are positioned between the layers. The other layer includes electrodes. When the electrodes are energized, they electrostatically attract the liquid droplets to create relative motion between the two layers.Type: ApplicationFiled: August 17, 2023Publication date: December 7, 2023Applicant: Massachusetts Institute of TechnologyInventor: Jakub T. KEDZIERSKI
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Patent number: 11777422Abstract: An actuator with a stack of thin layers operates by electrowetting droplets between the layers. The actuator includes a first layer structure and a second layer structure positioned adjacent to the first layer structure. One or more liquid droplets are pinned to one of the layers and are positioned between the layers. The other layer includes electrodes. When the electrodes are energized, they electrostatically attract the liquid droplets to create relative motion between the two layers.Type: GrantFiled: January 5, 2022Date of Patent: October 3, 2023Assignee: Massachusetts Institute of TechnologyInventor: Jakub T. Kedzierski
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Publication number: 20220216808Abstract: An actuator with a stack of thin layers operates by electrowetting droplets between the layers. The actuator includes a first layer structure and a second layer structure positioned adjacent to the first layer structure. One or more liquid droplets are pinned to one of the layers and are positioned between the layers. The other layer includes electrodes. When the electrodes are energized, they electrostatically attract the liquid droplets to create relative motion between the two layers.Type: ApplicationFiled: January 5, 2022Publication date: July 7, 2022Applicant: Massachusetts Institute of TechnologyInventor: Jakub T. Kedzierski
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Patent number: 7655557Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: GrantFiled: June 24, 2008Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Publication number: 20080254622Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: ApplicationFiled: June 24, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Patent number: 7411227Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: GrantFiled: April 19, 2006Date of Patent: August 12, 2008Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Patent number: 7250658Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.Type: GrantFiled: May 4, 2005Date of Patent: July 31, 2007Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Diane C. Boyd, Meikei Leong, Thomas S. Kanarsky, Jakub T. Kedzierski, Min Yang
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Patent number: 7183182Abstract: A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.Type: GrantFiled: September 24, 2003Date of Patent: February 27, 2007Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Meikei Ieong, Jakub T. Kedzierski
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Patent number: 7151023Abstract: A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.Type: GrantFiled: August 1, 2005Date of Patent: December 19, 2006Assignee: International Business Machines CorporationInventors: Hasan M. Nayfeh, Mahender Kumar, Sunfei Fang, Jakub T Kedzierski, Cyril Cabral, Jr.
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Patent number: 7056782Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: GrantFiled: February 25, 2004Date of Patent: June 6, 2006Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaran Surendra
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Patent number: 6927117Abstract: A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated with fabricating a CMOS structure containing silicide contacts and silicide gate metals.Type: GrantFiled: December 2, 2003Date of Patent: August 9, 2005Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Jakub T. Kedzierski, Victor Ku, Christian Lavoie, Vijay Narayanan, An L. Steegen
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Patent number: 6911383Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.Type: GrantFiled: June 26, 2003Date of Patent: June 28, 2005Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Diane C. Boyd, Meikei Ieong, Thomas S. Kanarsky, Jakub T. Kedzierski, Min Yang
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Publication number: 20040266076Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.Type: ApplicationFiled: June 26, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce B. Doris, Diane C. Boyd, Meikei Ieong, Thomas S. Kanarsky, Jakub T. Kedzierski, Min Yang