Abstract: An improved method for generating various wave functions for use in musical tone generation in FM synthesis so as to substantially reduce computational and storage requirements. The waveform desired to be used is mathematically modeled using piecewise linear approximation. A reduced number of coefficients of the piecewise linear approximation, representing the angles and offsets of the linear segments, are stored in memory.

Abstract: A new modem architecture that substantially minimizes the cost of adding features to the modem, and substantially minimizes the time overhead associated with the slave-like interface between the modem controller and the modem signal processor. The architecture enables the signal processor to directly access the controller's memory resources so that the signal processor can make most efficient use of its own internal expensive high-speed memory.

Abstract: An integrated circuit counter is capable of implementing a relatively high count while being testable using a relatively low number of clock cycles. A linear-feedback shift register (LFSR) having n bit positions is used as the counter. The feedback path of the shift register includes an exclusive OR (XOR) gate that couples selected bits back to the input of the register, in order to implement a 2.sup.n -1 counter. Combinatorial logic circuitry is included to test the counter in significantly less than 2.sup.n -1 clock cycles. This allows for implementing a testable "watchdog timer" that may be used to detect software runaway conditions in microprocessor systems, among other uses.

Abstract: A signal processing system includes means for performing a logic function on a multi-dimensional array of information stored in a memory. Typically, the memory stores two-dimensional video information (pixels), and the logic function is a discrete cosine transform (DCT), or other linear operation. The logic function is performed on both rows and columns of the information. In the prior art, this has required two memory spaces, so that information could be written into one memory while being read out of another memory. In the present invention, a single memory space is used to transpose the information between row and column format, by performing a read-modify-write operation on each memory location in a specified sequence.

Abstract: A technique for generating the tap-weight coefficients for a signal dispersion cancelling filter utilizes circuitry which is responsive to received signal samples and generates a time-ordered sequence of derived signal samples. The tap-weight coefficient circuitry includes filters which operate in response to this sequence. One such filter is responsive to the derived signal samples in a first portion of the sequence after the time-order of the derived signal samples therein is reversed and another filter is responsive to the derived signal samples in a second predetermined portion of the sequence. This technique is applicable to a variety of communications systems including television and is particularly suitable for integrated circuit implementation.