Abstract: A semiconductor device includes a pass transistor (28) electrically coupled to a driver transistor (16) by a common drain region (52). The pass transistor (28) includes the pass gate electrode (44) having a polycrystalline silicon layer (68). The driver transistor (16) includes a driver gate electrode (40) having a polycrystalline silicon layer (74). The dopant concentration in polycrystalline silicon layer (74) is greater than the dopant concentration in polycrystalline silicon layer (68). The differential and dopant concentration between the pass gate electrode (44) and the driver gate electrode (40) results in a greater current gain in the driver transistor (16) relative to the pass transistor (28). When incorporated into an SRAM memory cell (10), the driver transistor (16) and the pass transistor (28) provide greater cell stability by improving the immunity of the cell to electrical disturbance through the pass transistor (28).

Abstract: A semiconductor device (10) includes first and second electrically coupled MOS transistors (16, 28) in which the current gain of the second MOS transistor (16) is greater than the current gain of the first MOS transistor (28). Higher carrier mobility is obtained in the second MOS transistor (16) relative to the first MOS transistor (28) by fabrication of the second MOS transistor (16) as a buried channel device. The first MOS transistor (28) includes a gate electrode (44) of the second conductivity type separated from a channel region (46) of the first conductivity type by a gate electric layer (48). The second MOS transistor (16) includes a gate electrode (40) of a first conductivity type overlying a substrate (11) also of the first conductivity type. A channel surface layer (60) of a second conductivity type resides in the substrate (11 ) and is separated from the gate electrode (40) by a gate dielectric layer (58).

Abstract: An SRAM cell is formed such that pass channel-stop regions, which are adjacent to the pass transistors, have a higher doping concentration compared to the latch channel-stop regions that are adjacent to the latch transistors. In one embodiment, the pass channel-stop regions are formed using two channel-stop doping steps, whereas the latch channel-stop regions are formed during only one channel-stop doping step. The doping steps may be performed before or after field isolation is formed. The higher doping concentration causes the dopant from the pass channel-stop regions to extend laterally further from the edge of the field isolation compared to the latch channel-stop regions. The process can be adapted for use in almost any type of field isolation process.

Abstract: A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) overlie a single-crystal semiconductor substrate (12) and the channel region (46) of each driver transistor overlies a portion of an adjacent wordline. A portion of the thin-film layer (36, 36') makes contact to the single-crystal semiconductor substrate (12) adjacent to the opposite wordline. The channel and source-drain regions of first and second load transistors (15, 21) are formed in a second thin-film layer (64) which overlies the driver transistors (13, 19). The load transistors (15, 21) are cross-coupled to the driver transistors (13, 19) through common nodes (31, 33).

Abstract: A thin-film transistor having a thin-film channel region (20) inlaid in a recess (29) along the wall of a multi-layered insulating structure (14), and a gate electrode (12) electrically controlling current conduction in the thin-film channel (20) and separated therefrom by a gate dielectric layer (32). The multi-layered insulating structure (14) includes a spacing layer (28) which is withdrawn from the wall of the multi-layered insulating structure (14) and forms an inner wall of the recess (29). By residing in the recess (29), the thin-film channel region (20) is aligned to the multi-layered insulating structure (14) and the gate dielectric layer (32) separates exposed portions of the thin-film channel region (20) from the gate electrode (12). Thin-film source and drain regions (16, 18) are integral with the thin-film channel region (20) and are self-aligned to the multi-layered insulating structure (14).

Abstract: Defect-free field oxide isolation is achieved using a laminated layer (14) of thermal silicon dioxide and chemically vapor deposited silicon dioxide underneath a silicon nitride field oxidation mask (18). The laminated layer (14) of silicon dioxide is formed on a silicon substrate (12) and a layer of silicon nitride is then deposited over it. The silicon nitride is subsequently patterned to form a field oxidation mask (18) which defines isolation regions (22) within the silicon substrate (12). Field oxide (34) is grown in the isolation regions (22) of the silicon substrate (12) and the field oxidation mask (18) is subsequently removed.

Abstract: A transistor structure (10) has a substrate (12). A first transistor is formed within the substrate (12) having a source region (38), a drain region (30), and a gate electrode formed by a first spacer (26a). A second transistor is formed within the substrate (12) by the source region (38), a drain region (28), and a gate electrode formed by a second spacer (26a). A third transistor is formed overlying the first transistor. The third transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the first spacer (26a). A fourth transistor is formed overlying the second transistor. The fourth transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the second spacer (26a). The first, second, third, and fourth transistors may be interconnected to form a portion of a compact static random access memory (SRAM) cell.

Abstract: A method is provided for the formation of ultra-shallow boron doped regions in a semiconductor device. In one embodiment of the invention an N-type semiconductor substrate (15) is provided having a first P-type region formed therein. A dielectric layer (16) is formed on the substrate surface and a material layer (17) doped with fluorinated boron is formed on the dielectric layer (16). A second P-type region (22), characterized by a high dopant concentration at the substrate surface and a uniform junction profile, is formed in the substrate adjacent to the first P-type region by diffusing boron atoms from the material layer (17) through the dielectric layer (16) and into the substrate (15). The second P-type region (22) has a very shallow junction depth which is closer to the substrate surface than the first P-type region.

Abstract: A metal silicide interconnect (48, 92, 124) is formed in an integrated circuit using a sacrificial layer (30, 78, 108). In one embodiment a sacrificial layer of titanium nitride (30) is formed overlying a semiconductor substrate (12) and a polysilicon conductive member (20). The sacrificial titanium nitride layer (30) is then patterned and an underlying portion (40) of the semiconductor substrate (12), and a sidewall portion (42) of the polysilicon conductive member (20) are subsequently exposed. A metal layer (46) is deposited and then reacted with the exposed portion 40 of the semiconductor substrate (12) and the exposed sidewall (42) of the polysilicon conductive member (20) to form a metal silicide interconnect (48). The remaining portion of the sacrificial titanium nitride layer (38) is then removed after the metal silicide interconnect (48) has been formed without substantially altering the metal silicide interconnect (48).

Abstract: An SRAM cell is formed such that pass channel-stop regions, which are adjacent to the pass transistors, have a higher doping concentration compared to the latch channel-stop regions that are adjacent to the latch transistors. In one embodiment, the pass channel-stop regions are formed using two channel-stop doping steps, whereas the latch channel-stop regions are formed during only one channel-stop doping step. The doping steps may be performed before or after field isolation is formed. The higher doping concentration causes the dopant from the pass channel-stop regions to extend laterally further from the edge of the field isolation compared to the latch channel-stop regions. The process can be adapted for use in almost any type of field isolation process.

Abstract: A semiconductor memory cell (10) having a symmetrical layout is fabricated in first and second active regions (44, 46) of a semiconductor substrate (11). A first driver transistor (16) resides in the second active region (46), and a second driver transistor (20) resides in the first active region (44). The second driver transistor (20) has a gate electrode (55) overlying a portion of the first active region (44) and is electrically coupled to the second active region (46). A thin-film load transistor (18) resides over the first active region (44), the thin-film load transistor (18) has a thin-film channel layer (23) that overlies, and is aligned with, the gate electrode (55) of the second driver transistor (20). A second portion of the thin-film channel layer (23) extends away from the first active region (44) to form a Vcc node (36). A Vcc interconnect layer (82) overlies the thin-film load transistors and the driver transistors.

Abstract: A layer of silicon-germanium (57) allows electrical isolation structures, having reduced field oxide encroachment, to be formed without adversely effecting the adjacent active regions (64). A high etch selectivity between silicon-germanium and the silicon substrate (52) allows the silicon-germanium layer (57) to be removed, after field oxidation, without damaging the underlying active regions (64).

Abstract: A semiconductor device (10) and process provides first and second, electrically coupled MOS transistors (14, 16) in which the current gain of the second MOS transistor (16) is greater than the current gain of the first MOS transistor (14). First and second gate structures (23, 25) are formed on a gate dielectric layer (26) overlying a semiconductor substrate (12). The gate dielectric layer (26) has a uniform thickness in all regions. The current gain differential between the first and second MOS transistors (14, 16) is obtained by selectively forming a dielectric intrusion layer (42) under the gate structure (23) of the first MOS transistor (14), whereas the dielectric layer (26) underlying the gate structure (25) of the second MOS transistor (16) retains the uniform thickness. The dielectric intrusion layer (42) causes a higher channel resistance in the first MOS transistor (14) which retards the current gain in the first MOS transistor (14) relative to the current gain of the second MOS transistor ( 16).

Abstract: Dual field oxide isolation (34 & 42) is formed by oxidizing through a portion (44) of a silicon nitride layer (30), through an exposed portion (43) of a remaining portion (18) of a masking layer (16), and through an exposed portion (42) of a buffer layer (28), all of which overlie isolation regions (22) of the silicon substrate (12). The different portions vary the diffusion rate of oxygen so that different field oxide thicknesses are created in a single field oxidation cycle. Therefore, integrated circuits having both low voltage densely packed devices and high voltage devices can be fabricated on the same circuit.

Abstract: A process for forming isolation regions (20) having a self-aligned channel-stop (22) formed by implanting dopant atoms (24) through the isolation regions (22). An isolation mask (15) is formed over an active region (16) in a semiconductor substrate (10). The isolation mask can be constructed from a variety of materials including silicon nitride, silicon oxynitride, boron nitride, polysilicon, and germanium oxide. Thick isolation regions (20) are formed on either side of the isolation mask (15) and an ion implant process is carried out to form doped regions (22) in the substrate (10) immediately below the isolation regions (20). The isolation mask (15) prevents dopant atoms (24) from entering the active region (16) of the substrate (10).

Abstract: A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.

Abstract: A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) overlie a single-crystal semiconductor substrate (12) and the channel region (46) of each driver transistor overlies a portion of an adjacent wordline. A portion of the thin-film layer (36, 36') makes contact to the single-crystal semiconductor substrate (12) adjacent to the opposite wordline. The channel and source-drain regions of first and second load transistors (15, 21) are formed in a second thin-film layer (64) which overlies the driver transistors (13, 19). The load transistors (15, 21) are cross-coupled to the driver transistors (13, 19) through common nodes (31, 33).

Abstract: A semiconductor memory cell (10) including cross coupled CMOS transistors (12, 14) wherein an N-channel transistor (20) overlies a central portion of each of a first and second active regions (13, 13') at a position intermediate to two word lines (40, 42) which overlie end portions of the active regions (13, 13'). P-channel pull-up transistors (18, 22) overlie the N-channel transistors (16, 20) and share common intermediate gate electrodes (27, 29). Staggered bit line contacts (48, 50) are formed to each active region (13, 13') adjacent to each word line (40, 42) and opposite to the N-type transistors (16, 20). Staggered Vss contacts (52, 54) are provided to each active region (13, 13') adjacent to the word lines (40, 42) and opposite to the bit line contacts (48, 50). A Vss signal is electrically coupled to the N-channel transistors (16, 20) by a doped region (21) formed in the first and second active regions (13, 13' ) which cross under the word lines (40, 42).

Abstract: The present invention includes a static random access memory cell and a method of forming the memory cell, wherein the memory cell may comprise an active region and a first layer. The active region including a first segment, a second segment, and a third segment, wherein 1) the first segment has an adjacent end and a distal end; 2) the second segment is generally parallel to the first segment, and has an adjacent end and a distal end; and 3) the third segment is generally perpendicular to the first direction, wherein the adjacent end of the first segment lies near one end of the third segment, wherein the adjacent end of the second segment lies near the other end of the third segment. The first layer has the a shape similar to the active region except that the first layer does not lie over the first and second segments near the distal ends.

Abstract: A transistor structure (10) has a substrate (12). A first transistor is formed within the substrate (12) having a source region (38), a drain region (30), and a gate electrode formed by a first spacer (26a). A second transistor is formed within the substrate (12) by the source region (38), a drain region (28), and a gate electrode formed by a second spacer (26a). A third transistor is formed overlying the first transistor. The third transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the first spacer (26a). A fourth transistor is formed overlying the second transistor. The fourth transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the second spacer (26a). The first, second, third, and fourth transistors may be interconnected to form a portion of a compact static random access memory (SRAM) cell.