Abstract: A cluster of network flows is formed on the basis of a particular entity-to-entity relationship, and individual network flows within the cluster are further identified on an application-by-application basis to better characterize communications between two compute instances connected through a data network. By individually scoring network flows for each application with a variety of tools, and aggregating these individual scores into a composite score for the cluster of network flows, more accurate threat detections can be supported based on an increase in relevant threat data and a more complete view of risk factors.

Abstract: Systems and methods for transmitting source video (305) over a bandwidth-limited network (350). First, high frequency spectral content of the video is encoded into layer-1 data files (330). In parallel, frames of the video are downsampled (342) and compressed (333) using a lossy CODEC, to define layer-2 data files (335a, 335b) with high-frequency spectral content removed therefrom. The layer-1 and layer-2 data files are interleaved (345a, 345b) and transmitted over the network and are smaller than conventional lossy CODEC compressed files. After receipt, the layer-1 and layer-2 data files are deinterleaved. The layer-2 data is decompressed (353) and upsampled (362) to create a preliminary reconstructed video.

Abstract: In one approach for protecting a design, a plurality of implementations of the design are generated. Each implementation includes an identification function. One of the implementations is selected as a current implementation, and the current implementation is installed on one or more electronic systems. For each electronic system, a method determines whether or not the current implementation is an authorized version on the electronic system from an output value of the identification function. If in the current implementation is not an authorized version on the electronic system, a signal is output indicating that the current implementation is not an authorized version on the electronic system. Periodically, another one of the implementations is selected as a new current implementation, and the new current installation is used for installations on one or more electronic systems.

Abstract: Approaches for configuring a programmable integrated circuit (IC) are disclosed. Encrypted configuration data is input to the programmable IC, and the encrypted configuration data is stored in configuration memory of the programmable IC. As the encrypted configuration data is input, a determination is made as to whether or not the encrypted configuration data is authentic. In response to the encrypted configuration data being authentic, the encrypted configuration data is read from the configuration memory and decrypted, and the decrypted configuration data is stored back in the configuration memory.

Abstract: A lighting assembly for a vehicle, and in particular, an interior lighting assembly having a reduced profile using solid state illuminators is provided along with a method of construction thereof. The assembly includes a housing; a lens attached to the housing; a printed circuit board disposed between the housing and the lens; at least one light source attached in operable electrical communication to the printed circuit board; and a light blade. The light blade has opposite sides disposed between the printed circuit board and the lens. One of the sides has a first configuration of optics and the other of the sides has a second configuration of optics, wherein the first and second configurations of optics are different from one another.

Abstract: According to an embodiment, a method of preventing the alteration of a stored data value is disclosed. The method comprises coupling a first electronic fuse to an output control circuit; coupling a second electronic fuse to the output control circuit; decoding the states of the first electronic fuse and the second electronic fuse after a first processing step to generate a first decoded state; and decoding the states of the first electronic fuse and the second electronic fuse after a second processing step to generate a second decoded state different from the first decoded state; wherein the output control circuit maintains the second decoded state after an attempt to alter a state of an electronic fuse of the first electronic fuse and the second electronic fuse. A circuit for preventing the alteration of a stored data value is also described.

Abstract: An illuminated cup holder assembly constructed in accordance with one aspect of the invention facilitates the ability to see the cup holder in darkness while also providing an aesthetically pleasing, uniformly illuminated cup holder. The cup holder assembly includes a cup receptacle having an annular outer wall configured to receive a cup. A flexible, resilient finger extends radially inwardly from the annular wall, wherein the finger is configured to engage the cup to inhibit the cup from inadvertent movement in the cup receptacle. The finger has a translucent portion configured in communication with a light source to allow light to be emitted from the light source through the translucent portion into the cup receptacle.

Abstract: A lighting assembly for a vehicle, and in particular, an interior lighting assembly having a reduced profile using solid state illuminators is provided along with a method of construction thereof. The assembly includes a housing; a lens attached to the housing; a printed circuit board disposed between the housing and the lens; at least one light source attached in operable electrical communication to the printed circuit board; and a light blade. The light blade has opposite sides disposed between the printed circuit board and the lens. One of the sides has a first configuration of optics and the other of the sides has a second configuration of optics, wherein the first and second configurations of optics are different from one another.

Abstract: An illuminated cup holder assembly constructed in accordance with one aspect of the invention facilitates the ability to see the cup holder in darkness while also providing an aesthetically pleasing, uniformly illuminated cup holder. The cup holder assembly includes a cup receptacle having an annular outer wall configured to receive a cup. A flexible, resilient finger extends radially inwardly from the annular wall, wherein the finger is configured to engage the cup to inhibit the cup from inadvertent movement in the cup receptacle. The finger has a translucent portion configured in communication with a light source to allow light to be emitted from the light source through the translucent portion into the cup receptacle.

Abstract: An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.

Abstract: Dynamic cache architecture for a multi-processor array. The system includes a plurality of processors, with at least one of the processors configured as a parent processor, and at least one of the processors configured as a child processor. A data cache is coupled to the parent processor, and a dual port memory is respectively associated with each child processor part and parcel of a unified memory architecture. The parent processor may then dynamically distribute sub-cache components to dual-port memories based upon a scatter-gather work unit decomposition pattern. A parent cache controller reads, in response to a memory request from a child processor and an address translation pattern from the parent processor, a set of data from non-contiguous addresses of the data cache according to the address translation pattern, and writes the set of data to contiguous addresses of the dual port memory associated with the requesting child processor.

Abstract: A system and method of configuring a partially reconfigurable switch includes a pipelined partially reconfigurable switch interconnect may include a desired subset of connections in a switch interconnect, a partial bitstream defined for each of the desired subset of connections stored in a memory such as SRAM serving as a buffer, and a controller for cyclically applying the partial bitstream to the switch interconnect. The controller may determine a connection instance and duration for each client access of the switch interconnect in a synchronous manner. A clear to send (CTS), receive data (RD), destination address, and source address at each client may be sent with each partial bitstream for each desired subset of connections. The partially reconfigurable switch and a plurality of partially reconfigurable slot clients may be formed in a silicon backplane.

Abstract: A hardware stack (HSTACK) structure using programmable logic can include a look-up table (LUT) random access memory (RAM) circuit and circuitry within the LUT RAM circuit for propagating data upwards and downwards. The hardware structure can be arbitrarily assembled into a larger structure by adding stacks to a top portion, a bottom portion, or a portion between the top portion and the bottom portion. The hardware stack structure can further include a virtual stack (VSTACK) structure coupled to the HSTACK structure within a field programmable gate array (FPGA) fabric. The VSTACK can be arranged in the form of an appended peripheral memory and cache control for virtual extension to an HSTACK address space. The hardware stack structure can further include an auxiliary reset circuit.

Abstract: An FPGA system includes a combined shift register and look up table (LUT) forming a shift register LUT (SRL) that provides data write, reset and shift enable on a cell-by-cell basis. The data write and reset can be performed during FPGA operation without requiring a number of frames or columns of configuration memory cells to be reprogrammed, as with conventional SRAM cells. The shift enable provides for synchronization to facilitate the cell-by-cell write and reset.

Abstract: An instrument panel assembly (10) having a transparent intermediate substrate (42) inside its housing (16) on which is applied a phosphor coated indicia (40) for giving the appearance of a depth dimension when energized by a UV light source (36). Multiple intermediate substrates (42, 48) can be positioned at different level within the interior region of the housing (16), each containing various indicia (40, 46, 56, 58) which emits luminescent light when irradiated by the UV light source (36). Multiple UV light sources (36, 52) can be set to project UV radiation of different wavelengths into the housing (16) with each of the phosphor coated indicia (40, 46, 56, 58) being selected from material types which are responsive to only one of the various UV wavelengths, so that each indicia (40, 46, 56, 58) can be selectively energized to display warnings, information messages, or the like.

Abstract: A compliant marking tool for attachment to a fiber placement machine that is capable of marking detail locations on a work piece positioned on the fiber placement machine. The marking tool has a flexible member that is configured and adapted to bow and twist in response to the marking tool contacting the work piece. A holder is pivotably connected to the flexible member. A marking member is positioned in the holder and is capable of moving within the holder. The flexing of the flexible member along with the pivoting of the holder and the movement of the marking member allow the marking tool to follow the contours of the work piece and mark detail locations without damaging or at least minimizing the potential of damaging the work piece.