Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

Abstract: A circuit is described that detects high and low frequencies and additional clock frequencies and outputs a signal that indicates a high, a low frequency or an additional mode. When in the low frequency low frequency mode signals are regenerated free of any high frequency signals from appearing on the filtered low frequency clock line. The rising and falling edges of the input clock are low pass filtered separately and then combined to generate a low frequency clock or the additional input clock and that retains the input clock pulse width and duty cycle.

Abstract: An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.

Abstract: An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.

Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

Abstract: An MIPI controller using undefined or unknown MIPI LP codes to select among several destinations is disclosed. The codes may be intercepted and decoded to select among analog switches that, in one illustrative embodiment, connects the MIPI clock and data signals to a first or a second or to both displays of a mobile phone. In other applications additional destinations may also be selected.

Abstract: A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mode between the sending of data. Word data bits are framed and sent along with clock pulses that define when the bits may be reliably received. High speed, typically, CML logic is used for the transmission line drivers and together with the clock pulse, a data word is sent faster than the computer system can send the next word to the serializer/deserializer. The disclosure frames the word and detects the word end, whereupon the system is placed into the standby mode. In addition the serializer/deserializers may be placed in a master/slave arrangement where the slave can be arranged to use the master's clock to send word data bits back to the master.

Abstract: A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mode between the sending of data. Word data bits are framed and sent along with clock pulses that define when the bits may be reliably received. High speed, typically, CTL logic is used for the transmission line drivers and together with the clock pulse, a data word is sent faster than the computer system can send the next word to the serializer/deserializer. The disclosure frames the word and detects the word end, whereupon the system is placed into the standby mode. In addition the serializer/deserializers may be placed in a master/slave arrangement where the slave can be arranged to use the master's clock to send word data bits back to the master.

Abstract: A circuit is described that detects high and low frequencies and additional clock frequencies and outputs a signal that indicates a high, a low frequency or an additional mode. When in the low frequency low frequency mode signals are regenerated free of any high frequency signals from appearing on the filtered low frequency clock line. The rising and falling edges of the input clock are low pass filtered separately and then combined to generate a low frequency clock or the additional input clock and that retains the input clock pulse width and duty cycle.

Abstract: A serializing/deserializing interface is discussed for reducing the number of connections and signals being carried over a flex cable as would be found in a hand held mobile device. In particular the interface interleaves data, multiplexes data and multiplexes control for a number of I/O devices. For example those I/O devices might include an LCD display, a camera, a keypad and a GPIO (general purpose I/O) device.

Abstract: A serializer and a deserializer are disclosed and shown operating singly or as a pair. The invention operates independently from any outside system reference clock. The inventive system provides an internal bit clock that serializes the data when sending and de-serializes the data when receiving. A bit clock or pulse travels with the data word bits to define when a bit is stable. The system uses word boundary bits operating with a bit clock to distinguish different data words, as described in the parent application. The system operates either synchronously or asynchronously with the base computer or other such digital system, including I/O devices. The invention finds use where new data to be sent is strobed into the serializer, but also where a change in the data bit content itself will cause the changed data to be loaded into the serializer and sent bit by bit. The system operates where new data is strobed or loaded by the serializer (not the base computer system) when the last data word has been sent.

Abstract: A bi-direction voltage level translating switch that connects a higher voltage circuit to a lower voltage circuit without using a direction signal disclosed. The drive circuit for the gate of an MOS switch acts to clamp the lower voltage side of the translating switch limiting the lower voltage to a level compatible with the lower voltage circuitry connected to the lower voltage side. A pull up circuit is connected to the higher voltage side of the switch and further defines a threshold lower than the lower voltage. When the signal reaches the threshold the pull up circuit pull the higher voltage side up to the higher voltage. Again the drive on the gate of the switch prevents that higher voltage from reaching the lower voltage side. When the lower voltage side drives, through an on switch, the higher voltage side low, the pull up circuit is designed to be overcome by the lower voltage drive circuitry so that the higher voltage side goes low.

Abstract: A bi-direction voltage level translating switch that connects a higher voltage circuit to a lower voltage circuit without using a direction signal disclosed. The drive circuit for the gate of an MOS switch acts to clamp the lower voltage side of the translating switch limiting the lower voltage to a level compatible with the lower voltage circuitry connected to the lower voltage side. A pull up circuit is connected to the higher voltage side of the switch and further defines a threshold lower than the lower voltage. When the signal reaches the threshold the pull up circuit pull the higher voltage side up to the higher voltage. Again the drive on the gate of the switch prevents that higher voltage from reaching the lower voltage side. When the lower voltage side drives, through an on switch, the higher voltage side low, the pull up circuit is designed to be overcome by the lower voltage drive circuitry so that the higher voltage side goes low.

Abstract: A full swing CMOS output buffer circuit (20,30,40,50) isolates incompatible power supply circuits such as 3.3 v standard and 5 v standard subcircuits, and isolates power supply rails of quiet or powered down buffer circuits from the common external bus. The pullup output transistor (PMOS1) is fabricated in a well (NWELL) of N type carrier semiconductor material formed in a substrate (PSUB) of P type carrier semiconductor material. A P channel NWELL isolation switch transistor (PW1) has a primary current path coupled between the well (NWELL) and high potential power rail (VCC) and a control gate node coupled to the control gate node of the pullup output transistor (PMOS1) for operating substantially in phase. The NWELL isolation switch transistor (PW1) isolates the pullup output transistor (PMOS1) well (NWELL) from the high potential power rail (VCC).

Abstract: An output buffer circuit (10,11) is protected by a short circuit protection circuit (12) from short circuit conditions at the output by detecting occurrence of a short circuit condition of the output (V.sub.OUT) shorted to either the high or low potential power rails (V.sub.CC, GND) and by tristating the output buffer circuit upon detecting the short circuit condition. Detection of a short circuit condition is accomplished by sensing and comparing the respective states of signals at the input (V.sub.IN) and output (V.sub.OUT) and detecting occurrence of an out of state condition between the input and output. If the out of state condition is sensed for a sensing time delay period (tC1, tC2) longer than characteristic propagation delay times (tpHL, tpLH), a short circuit sensing signal (VLO, VHI) is generated.

Abstract: CMOS output circuit improvements control output signal rise and fall times during transition between high and low potential levels at the output (V.sub.OUT). A plurality of pulldown predriver resistors (R1.sub.N, R2.sub.N, R3.sub.N) are coupled in parallel paths in the pulldown predriver circuit. Respective resistance values slow turn on of the output pulldown driver transistor (N1) for achieving a plurality of different fall times. A plurality of pulldown predriver switch transistors (PS1, PS2, PS3) are respectively coupled in series with the pulldown predriver resistors (R1.sub.N, R2.sub.N, R2.sub.N). The switch transistors (PS1, PS2, PS3) have respective control inputs (V.sub.S1, V.sub.S2, V.sub.S3) for selecting respective parallel paths containing the different pulldown predriver resistors (R1.sub.N, R2.sub.N, R3.sub.N). A plurality of pullup predriver resistors (R1.sub.P, R2.sub.P, R3.sub.P) are coupled in parallel paths in the pullup predriver circuit.

Abstract: A CMOS oscillator integrated circuit in a Pierce crystal oscillator circuit configuration operates at oscillating frequencies over a wide band frequency range. A single inverter stage (I1) is coupled between the oscillator input (OSC IN) and the oscillator output (OSC OUT). An oscillator feedback circuit coupled between the oscillator output and oscillator input incorporates an oscillator crystal (XTAL). A pullup gain network (PNET) provides a plurality of different parallel pullup gain paths between the pullup transistor (P1) of the inverter stage (I1) and the high potential power rail (V.sub.CC). The pullup gain paths have different pullup gain resistances (RP2, RP3, . . . RPN) in the respective pullup gain paths for implementing different amplifying gains (A.sub.N) by the inverter stage (I1). Digitally addressable pullup gain switches (P2, P3, . . . PN) are coupled in respective pullup gain paths for selecting different gain paths and different amplifying gains (A.sub.N).