Patents by Inventor James D. Gallia
James D. Gallia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7638412Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.Type: GrantFiled: July 24, 2007Date of Patent: December 29, 2009Assignee: Texas Instruments IncorporatedInventors: James D. Gallia, Srikanth Krishnan, Anand T. Krishnan
-
Patent number: 7262468Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.Type: GrantFiled: December 28, 2001Date of Patent: August 28, 2007Assignee: Texas Instruments IncorporatedInventors: James D. Gallia, Srikanth Krishnan, Anand T. Krishnan
-
Patent number: 6708303Abstract: A scan circuit (10) has a scan data input (17), a normal data input (18), a clock input (22), a scan enable input (19), a normal data output (23), and a scan data output (24). The scan circuit includes a multiplexer (27) having two data inputs respectively coupled to the scan data input and normal data input of the scan circuit, having a control input coupled to the scan enable input of the scan circuit, and having an output. The scan circuit also includes a D-type flip-flop (28) having a data input coupled to the output of the multiplexer, having a clock input coupled to the clock input of the scan circuit, and having a data output serving as the normal data output of the scan circuit. The scan circuit further includes a gate (29) having a first input coupled to an output of the flip-flop, having a second input coupled to the scan enable input of the scan circuit, and having an output which serves as the scan data output of the scan circuit.Type: GrantFiled: February 26, 1999Date of Patent: March 16, 2004Assignee: Texas Instruments IncorporatedInventor: James D. Gallia
-
Publication number: 20030122190Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.Type: ApplicationFiled: December 28, 2001Publication date: July 3, 2003Applicant: Texas Instruments IncorporatedInventors: James D. Gallia, Srikanth Krishnan, Anand T. Krishnan
-
Publication number: 20030094642Abstract: An integrated circuit includes several circuit portions coupled between two rails that carry respective different voltage potentials. Each circuit portion includes a relatively small capacitance, coupled in series with a resistance which is sufficient to effect substantial limiting of the magnitude of any leakage current that may flow through the capacitor.Type: ApplicationFiled: November 16, 2001Publication date: May 22, 2003Inventors: Theodore W. Houston, James D. Gallia
-
Patent number: 6563158Abstract: An integrated circuit includes several circuit portions coupled between two rails that carry respective different voltage potentials. Each circuit portion includes a relatively small capacitance, coupled in series with a resistance which is sufficient to effect substantial limiting of the magnitude of any leakage current that may flow through the capacitor.Type: GrantFiled: November 16, 2001Date of Patent: May 13, 2003Assignee: Texas Instruments IncorporatedInventors: Theodore W. Houston, James D. Gallia
-
Patent number: 5173623Abstract: BiCMOS circuits are disclosed which achieve high speed operation under a wide range of loading conditions. The circuits are capable of providing a full output voltage swing and dissipate virtually no static power. The BiCMOS circuits are implemented using both CMOS and bipolar transistors. The circuits use their output signal to control the CMOS transistors that overcome bipolar output drops for full swing operation. The same fundamental CMOS and bipolar configurations can be applied to implement complex and simple logic functions such as NAND, NOR, AND, or OR operations.Type: GrantFiled: February 27, 1992Date of Patent: December 22, 1992Assignee: Texas Instruments IncorporatedInventors: Kwok K. Chau, James D. Gallia, Ashwin H. Shah
-
Patent number: 5126973Abstract: A redundancy scheme for a memory device, as well as a method for developing a redundancy scheme, resulting in improved repairability for given space constraints. A memory device is formed with a plurality of data blocks having individual input/output paths. Each block comprises an array of memory cells arranged in addressable rows and columns along row lines and column lines. The array is configured in sub-blocks each comprising a plurality of the memory cells. The device includes row address circuitry for selecting a row of the memory cells, column address circuitry for selecting a column of the memory cells and address repair circuitry. The address repair circuitry is configurable to render a first portion of a first of the columns of cells responsive to the address of a portion of a second of the columns of cells. There is also provided a method for eliminating a defect in a memory device having a logical data block formed with addressable rows and columns of memory cells.Type: GrantFiled: February 14, 1990Date of Patent: June 30, 1992Assignee: Texas Instruments IncorporatedInventors: James D. Gallia, Jim Childers
-
Patent number: 5107147Abstract: A BiCMOS gate array base is disclosed which is capable of simultaneously implementing a BiCMOS gate and/or a multitude of CMOS gates. The cell has symmetry about 1 axis, with the bipolar devices in the center and equally accessible for interconnect by two CMOS sections. The cell allows half-cell macro circuit blocks to be placed into the base cell in an independent and flexible fashion. The same macro can be placed in either CMOS section because of the mirror symmetry. The base cell can be divided into 2 units of macro placement. The number of devices in the CMOS section is variable. This cell architecture can be extended to other mixed technologies.Type: GrantFiled: March 28, 1991Date of Patent: April 21, 1992Assignee: Texas Instruments IncorporatedInventors: Ah-Lyan Yee, James D. Gallia
-
Patent number: 5019888Abstract: An output buffer (26) comprises a plurality of transistors (28) arranged in parallel between an output pin (34) and ground (38). Resistors (30) are connected in series between the drain (30) of the transistors (28) and the output pin (34) to ensure that an electrostatic discharge generated through normal handling will be distributed substantially equally through each of the transistors (28), thus preventing damage to the output buffer (26).Type: GrantFiled: July 23, 1987Date of Patent: May 28, 1991Assignee: Texas Instruments IncorporatedInventors: David B. Scott, Patrick W. Bosshart, James D. Gallia
-
Patent number: 4723228Abstract: Column decoding is performed using multiply decoded subsets of column address bits bussed across the array to multiple first stage and second stage column multiplexers. That is, for example, in an 8k by 9 memory wherein each subarray contains 16 selectable columns at each bit position, two of the address bits would be fully decoded to provide four buss lines across the chip. Each column has a primary sense amplifier, controlled by one of these four decoded lines. The outputs of each set of four primary sense amplifiers are multiplexed into a secondary sense amplifier, (preferably on a local three-scale buss) and the output of each secondary sense amplifier is selected or deselected by four buss lines which are the decoded signals corresponding to the other two address bits which select one of 16 columns. Preferably multiplexing of the output of the secondary sense amplifiers is accomplished by a three-state buffer, so that the output of these buffers can be accomplished as a wired-or function.Type: GrantFiled: August 31, 1983Date of Patent: February 2, 1988Assignee: Texas Instruments IncorporatedInventors: Ashwin H. Shah, James D. Gallia, Shivaling S. Mahant-Shetti
-
Patent number: 4604727Abstract: A memory including various selectively configurable peripherals which provide on-chip low-level control features and a configuration RAM storing bits which both provide unclocked full logic-level outputs to control the selectively configurable peripherals and can also be accessed and read out. That is, each cell in the configuration RAM has two output modes: a digital continuous output, which is provided as a continuous control signal to various peripheral circuits and a selectable analog output which is used to read the information stored in the configuration RAM.Type: GrantFiled: August 31, 1983Date of Patent: August 5, 1986Assignee: Texas Instruments IncorporatedInventors: Ashwin H. Shah, Pallab K. Chatterjee, James D. Gallia, Shivaling S. Mahant-Shetti
-
Patent number: 4601019Abstract: A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally received column address and the stored defective-column-address is found, the sense amplifier for the bit position which contains that defective column is disabled, and the output of the redundant column (selected by whichever word line is activated) is multiplexed into the I-O buss. Thus, before the row address signal has even been decoded, the defective column has been disabled and one of the redundant columns has effectively been substituted. This configuration means that it is not necessary to have one redundant column for every bit position, but each redundant column can substitute for a defective column in any bit position, and more than one defective column in a single bit position can each be replaced.Type: GrantFiled: August 31, 1983Date of Patent: July 15, 1986Assignee: Texas Instruments IncorporatedInventors: Ashwin H. Shah, James D. Gallia, I-Fay Wang, Shivaling S. Mahant-Shetti