Patents by Inventor James D. Guilford

James D. Guilford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200280432
    Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 3, 2020
    Inventors: Gilbert M. WOLRICH, Kirk S. YAP, Vinodh GOPAL, James D. GUILFORD
  • Patent number: 10763894
    Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Sudhir K. Satpathy, Sanu K. Mathew
  • Patent number: 10725779
    Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Kirk S. Yap, Gilbert M. Wolrich, James D. Guilford, Vinodh Gopal, Erdinc Ozturk, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • Patent number: 10691458
    Abstract: A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Kirk S. Yap, Gilbert Wolrich, James D. Guilford, Vinodh Gopal, Erdinc Ozturk, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • Patent number: 10694217
    Abstract: A processing device includes compression circuitry to encode an input stream with an encoding that translates multiple symbols of fixed length into multiple codes of variable length between one and a maximum length, to generate a compressed stream. The compression circuitry is to: determine at least a first symbol of the multiple symbols having a first code that exceeds the maximum length; identify a short code of the multiple codes that is to be lengthened to provide an increased encoding capacity for the at least the first symbol; generate multiple code-length converted values including to increase the length of the short code to the maximum length and decrease, to the maximum length, a length of the first code of the at least the first symbol; and generate, with use of the set of code-length converted values, the compressed stream at the output terminal.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Sudhir K. Satpathy, Vinodh Gopal, James D. Guilford, Sanu K. Mathew, Vikram B. Suresh
  • Patent number: 10684855
    Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Erdinc Ozturk, Wajdi K. Feghali, Gilbert M. Wolrich, Martin G. Dixon
  • Patent number: 10666288
    Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. In hardware, an input buffer stores incoming input records from a compressed stream. A plurality of decoders decode at least one input record from the input buffer out output an intermediate record from the decoded data and a subset of the plurality of decoders to output a stream of literals. Finally, a reformat circuit formats an intermediate record into one of two types of tokens.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Sean M. Gulley, Kirk S. Yap
  • Patent number: 10649774
    Abstract: A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Wajdi K. Feghali, Erdinc Ozturk, Gilbert M. Wolrich, Martin G. Dixon, Mark C. Davis, Sean P. Mirkes, Alexandre J. Farcy, Bret L. Toll, Maxim Loktyukhin
  • Patent number: 10635338
    Abstract: Technologies for high-ratio compression with heterogeneous history buffers include a computing device having an accelerator complex with a large history buffer and a small history buffer. The large history buffer has a larger size than the small history buffer. For example, the small history buffer may be 32 kilobytes and the large history buffer may be 64 kilobytes, 1 megabyte, or larger. The large history buffer is coupled to a large-buffer compare core that searches for matches in the large history buffer, finds a best match, and forwards the best match to a small-buffer compare core. The small-buffer compare core searches the small history buffer for matches, receives the match forwarded from the large-buffer compare core, and determines a best match from the matches in the small history buffer and the forwarded match. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford
  • Patent number: 10628068
    Abstract: Technologies for database acceleration include a computing device having a database accelerator. The database accelerator performs a decompress operation on one or more compressed elements of a compressed database to generate one or more decompressed elements. After decompression of the compressed elements, the database accelerator prepares the one or more decompressed elements to generate one or more prepared elements to be processed by an accelerated filter. The database accelerator then performs the accelerated filter on the one or more prepared elements to generate one or more output elements. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Kirk S. Yap, Simon N. Peffers, Daniel F. Cutter
  • Publication number: 20200099958
    Abstract: A processing device includes compression circuitry to encode an input stream with an encoding that translates multiple symbols of fixed length into multiple codes of variable length between one and a maximum length, to generate a compressed stream. The compression circuitry is to: determine at least a first symbol of the multiple symbols having a first code that exceeds the maximum length; identify a short code of the multiple codes that is to be lengthened to provide an increased encoding capacity for the at least the first symbol; generate multiple code-length converted values including to increase the length of the short code to the maximum length and decrease, to the maximum length, a length of the first code of the at least the first symbol; and generate, with use of the set of code-length converted values, the compressed stream at the output terminal.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Inventors: Sudhir K. Satpathy, Vinodh Gopal, James D. Guilford, Sanu K. Mathew, Vikram B. Suresh
  • Patent number: 10581594
    Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert M. Wolrich, Kirk S. Yap, Vinodh Gopal, James D. Guilford
  • Patent number: 10528539
    Abstract: In an example, there is disclosed an apparatus, comprising: a data store comprising a hash table having for at least some rows a hash entry indexed by a hash value, and comprising a hash chain of one or more pointers to a history buffer, and a spill counter; and one or more logic elements, including at least one hardware logic element, comprising a data compressor to: inspect a string0 comprising n bytes at position p in a data file; get the spill counter from a hash entry corresponding to string0; inspect a string1 comprising n bytes at p+k, wherein k is a positive integer; get the spill counter from a hash entry corresponding to string1; determine that the spill counter for string1 is less than the spill counter for string0; and search a chain1 (the hash chain of a hash entry corresponding to string1) for a matching string of size at least n+k with an offset of ?k.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Daniel Cutter
  • Patent number: 10509580
    Abstract: Methods and apparatuses relating to memory compression and decompression are described, including a memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match. When indices for multiple sections are the same, an entry in the dictionary may be updated with the value of the section that is most recent, in the same order as in the block of data.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Kirk S. Yap, Vinodh Gopal, James D. Guilford, Sean M. Gulley
  • Patent number: 10496703
    Abstract: Techniques and apparatus for discrete compression and decompression processes are described. In one embodiment, for example, an apparatus may include at least one memory and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a compression configuration to compress source data, generate discrete compressed data comprising at least one high-level block comprising a header and at least one discrete block based on the compression configuration, and generate index information for accessing the at least one discrete block. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: December 3, 2019
    Assignee: INTEL CORPORATION
    Inventors: Vinodh Gopal, James D. Guilford
  • Publication number: 20190363733
    Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 28, 2019
    Inventors: Vinodh Gopal, James D. Guilford, Sudhir K. Satpathy, Sanu K. Mathew
  • Publication number: 20190332378
    Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 31, 2019
    Inventors: Kirk S. YAP, Gilbert M. WOLRICH, James D. GUILFORD, Vinodh GOPAL, Erdinc OZTURK, Sean M. GULLEY, Wajdi K. FEGHALI, Martin G. DIXON
  • Patent number: 10404836
    Abstract: In an embodiment, a processor comprises a plurality of processing cores and a compression accelerator to compress an input stream comprising a first data block and a second data block. The compression accelerator comprises a first compression engine to compress the first data block; and a second compression engine to update state data for the second compression engine using a sub-portion of the first data block; and after an update of the state data for the second compression engine using the sub-portion of the first data block, compress a second data block using the updated state data for the second compression engine. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Daniel F. Cutter
  • Patent number: 10379853
    Abstract: A processor is described having an instruction execution pipeline having a functional unit to execute an instruction that compares vector elements against an input value. Each of the vector elements and the input value have a first respective section identifying a location within data and a second respective section having a byte sequence of the data. The functional unit has comparison circuitry to compare respective byte sequences of the input vector elements against the input value's byte sequence to identify a number of matching bytes for each comparison. The functional unit also has difference circuitry to determine respective distances between the input vector's elements' byte sequences and the input value's byte sequence within the data.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich
  • Patent number: 10379854
    Abstract: Processor instructions for determining two minimum and two maximum values and associated apparatus and methods. The instructions include various 2MIN instructions for determining the two smallest values among three or four input values and 2MAX instructions for determining the two largest values among three or four input values. The 2MIN instructions employ two operands, with the first operand in some of the variations storing concatenated min1 and min2 values in a first register and a scr2 comparison value or two src2 concatenated src2 values in a second register. Comparators are used to implement hardware logic for determining whether the scr2 value(s) is/are less than each of min1 and min2. Based on the hardware logic, the smallest two values among min1, min2, and src2 (or both src2 values) are stored as concatenated values in the first register. The 2MAX instructions are implemented in a similar manner, except the comparisons are whether the scr2 value(s) is/are greater than each of max1 and max2 values.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford