Abstract: Disclosed is an assay device which comprises a liquid sample addition zone, a reagent zone, a detection zone, and a wicking zone, all defining a fluid flow path. The device further comprises a reagent addition zone along and in fluid communication with the fluid flow path downstream of the sample addition zone and upstream of the detection zone. An interrupting wash is added at this reagent addition zone in accordance with the method of the subject invention to control sample volume. The interrupting wash fluid is added at a predetermined fill volume on the chip device and also serves to wash the detection channel and fill the remaining chip volume.

Abstract: In one embodiment, a method is provided. The method of this embodiment may include receiving an indication that a first device has been granted access to a bus. In response, at least in part, to the indication, a signal may be provided that may result in the coupling of a signal line of a second device to the bus. After the provision of the signal, the first device may configure the second device. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.

Abstract: In one embodiment, a method is provided. The method of this embodiment may include receiving an indication that a first device has been granted access to a bus. In response, at least in part, to the indication, a signal may be provided that may result in the coupling of a signal line of a second device to the bus. After the provision of the signal, the first device may configure the second device. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: An input/output device on a bus may be controlled to enable advanced features such as RAID to be implemented on a system board which is not otherwise specially adapted in any fashion to implement such features. The system board need not include, in its basic configuration, a host bus adapter such as one using an I/O processor, or standard BIOS instructions which assist in the implementation of the advanced features. The advanced features may be implemented by plugging an appropriate host bus adapter into an appropriate bus slot to provide the advanced functionality. By using special logic and signals on the host bus adapter, the advanced functionality may be achieved in a platform independent system board implementation and without the added cost of an I/O device on the host bus adapter.

Abstract: A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.

Abstract: A cache SRAM connector assembly comprising a connector, a number of latches, and a number of high performance switches, is provided to a computer system. The connector removably connects either asynchronous or burst cache SRAM to a processor bus. The latches store cache access addresses being driven on a number of address lines of the processor bus. The high performance switches being coupled to both the latches and the address lines of the processor bus selectively provide the cache SRAM with latched access addresses as required by asynchronous cache SRAM or directly driven access addresses on the processor bus as required by burst cache SRAM.

Abstract: A heat sink apparatus dissipates heat from an integrated circuit which is connected to a printed circuit board. A support member is connected to the circuit board for supporting the integrated circuit with respect to the circuit board. A metal tab in thermal communication with the integrated circuit extends from the support member in a plane substantially parallel to the circuit board. An electrically insulating thermally conductive compressible pad is positioned in contact with the metal tab for receiving heat from the tab when compressed. A thermally conductive housing is positioned adjacent the pad for compressing the pad against the tab and for receiving heat from the pad when compressed. The housing includes a plurality of fins extending therefrom for heat dissipation. A method for dissipating heat from an integrated circuit which is connected to a printed circuit board is also provided.

Abstract: A method for producing heterocyclic aluminum compounds of the formula: ##STR1## where n is 0 to 1, by reacting aluminum chloride with an aliphatic polyhydric alcohol having from 2 to 6 carbon atoms and having hydrogen, hydroxy, or low alkyl groups on carbon atoms which are spaced apart by no more than one intervening carbon atom, which is useful as an anti-perspirant.

Abstract: A clear or translucent cosmetic stick containing an acidic material and a reactive solvent, using dibenzyl monosorbitol acetal as the gelling agent an N-(2-hydroxyethyl) acetamide as the stabilizing agent. In particular are included antiperspirant sticks with an astringent metal salt and also containing lower aliphatic mono- and dihydric alkanols.

Abstract: Clear gel antiperspirant sticks comprising (a) about 37 to 94 percent by weight of a non-reactive alkanol, (b) about 1 to 10 percent of dibenzyl monosorbitol acetal, (c) 0 to 25 percent of an emollient, (d) about 5 to 25 percent of an antiperspirant active compound, and (e) about 0 to 3 percent of a C.sub.12 to C.sub.20 fatty acid.

Abstract: Antiperspirant stick compositions containing dibenzyl monosorbitol acetal in the presence of acidic antiperspirant-active salts, which are stable for extended periods of time at elevated temperatures; said sticks comprising (a) about 1 to 80 percent by weight of a reactive solvent; (b) about 0 to 75 percent by weight of a non-reactive solvent; (c) about 1 to 10 percent by weight of dibenzyl monosorbitol acetal; (d) about 0 to 35 percent by weight of an emollient; (e) about 5 to 25 percent by weight of an antiperspirant-active compound; (f) about 0 to 2.5 percent by weight of a C.sub.12 -C.sub.20 fatty acid; and (g) 0.05 to 15 percent by weight of a gel stabilizer; said gel stabilizer being a member of the group consisting of magnesium sulfate, zinc acetate and hexamethylenetetramine and mixtures thereof.

Abstract: This invention concerns novel 3-[(3-alkylamino-2-hydroxypropoxy)phenyl]-1,2-propanediols of the formula: ##STR1## wherein R is selected from the group consisting of straight or branched-chain lower alkyls (C.sub.1 -C.sub.6) and cycloalkyls (C.sub.1 -C.sub.6); R.sub.1 and R.sub.2 are selected from the group consisting of hydrogen and 2,3-dihydroxypropyl, with the proviso that R.sub.1 and R.sub.2 may not be the same; and R.sub.3 is selected from the group consisting of lower alkyls (C.sub.1 -C.sub.4) and lower alkoxys (C.sub.1 -C.sub.4); and the acid addition salts thereof. These novel compounds are useful as antiarrhythmic agents and .beta.-andrenergic blockers in mammals.This invention also concerns novel compounds of the formula ##STR2## wherein R.sub.1 and R.sub.2 are selected from the group consisting of hydrogen and 2,3-dihydroxypropyl, with the proviso that R.sub.1 and R.sub.2 may not be the same; R.sub.3 is selected from the group consisting of lower alkyls (C.sub.1 -C.sub.4) and lower alkoxys (C.sub.