Patents by Inventor James Dennis Dodrill
James Dennis Dodrill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11586445Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.Type: GrantFiled: November 27, 2019Date of Patent: February 21, 2023Assignee: Arm LimitedInventors: Shardendu Shekhar, Andy Wangkun Chen, Anil Kumar Baratam, James Dennis Dodrill, Yew Keong Chong
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Patent number: 11520658Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.Type: GrantFiled: October 31, 2019Date of Patent: December 6, 2022Assignee: Arm LimitedInventors: Joel Thornton Irby, Wendy Arnott Elsasser, Mudit Bhargava, Yew Keong Chong, George McNeil Lattimore, James Dennis Dodrill
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Publication number: 20210157603Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.Type: ApplicationFiled: November 27, 2019Publication date: May 27, 2021Inventors: Shardendu Shekhar, Andy Wangkun Chen, Anil Kumar Baratam, James Dennis Dodrill, Yew Keong Chong
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Publication number: 20210133027Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.Type: ApplicationFiled: October 31, 2019Publication date: May 6, 2021Inventors: Joel Thornton IRBY, Wendy Arnott ELSASSER, Mudit BHARGAVA, Yew Keong CHONG, George McNeil LATTIMORE, James Dennis DODRILL
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Patent number: 10641822Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.Type: GrantFiled: November 20, 2017Date of Patent: May 5, 2020Assignee: ARM LimitedInventors: Satheesh Balasubramanian, Shardendu Shekhar, James Dennis Dodrill, Sainarayanan Karatholuvu Suryanarayanan
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Patent number: 10187063Abstract: Various implementations described herein are directed to a sequential logic device having multiple stages. The sequential logic device may include a first stage having first transistors that are arranged to receive a data input signal and a clock signal and provide a first signal and a second signal based on the data input signal and the clock signal. The sequential logic device may include a second stage having second transistors that are arranged to receive the first signal from the first stage and provide an inverted first signal to a gate of a first pass transistor. The first pass transistor may allow the second signal to pass from the first stage to a second pass transistor based on the inverted first signal, and the second pass transistor may allow the second signal to pass from the first pass transistor to ground based on the clock signal.Type: GrantFiled: November 29, 2017Date of Patent: January 22, 2019Assignee: ARM LimitedInventors: Amanda Ashley Scantlin, Anil Kumar Baratam, James Dennis Dodrill, Susan Marie Graham
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Patent number: 10020031Abstract: Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.Type: GrantFiled: January 9, 2017Date of Patent: July 10, 2018Assignee: ARM LimitedInventors: Yew Keong Chong, Andy Wangkun Chen, Sriram Thyagarajan, Gus Yeung, James Dennis Dodrill
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Publication number: 20180074116Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.Type: ApplicationFiled: November 20, 2017Publication date: March 15, 2018Inventors: Satheesh Balasubramanian, Shardendu Shekhar, James Dennis Dodrill, Sainarayanan Karatholuvu Suryanarayanan
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Patent number: 9912338Abstract: A circuit to sample an input signal in an asynchronous clock domain. The apparatus includes a first latch configured to favor resolving to a logical high level and a second latch configured to favor resolving to a logical low level. The circuit includes a pullup pMOSFET, and first and second pMOSFETs. The first pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to a first input port of the first latch, and a drain terminal coupled to a second output port of the second latch. The second pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to the second output port of the second latch, and a drain terminal coupled to the first input port of the first latch.Type: GrantFiled: April 7, 2017Date of Patent: March 6, 2018Assignee: ARM LimitedInventors: James Dennis Dodrill, Paul Christopher de Dood
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Patent number: 9892220Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.Type: GrantFiled: March 13, 2017Date of Patent: February 13, 2018Assignee: ARM LimitedInventors: Marlin Wayne Frederick, Jr., Karen Lee Delk, Lena Ahlen, James Dennis Dodrill
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Patent number: 9825636Abstract: An apparatus for synchronizing an input signal that is asynchronous to a clock signal received by the apparatus. The apparatus comprising selection circuitry configured to select the input signal and to generate a pair of intermediate signals associated with the selected input signal. The apparatus also comprising resolution circuitry configured to provide differential signals based on the pair of intermediate signals and to resolve meta-stability associated with the differential signals. The apparatus also comprising arbiter circuitry configured to determine a dominant value associated with the differential signals and to generate an intermediate output signal based on the determination. The apparatus further comprising latching circuitry configured to generate an output signal based on the intermediate output signal.Type: GrantFiled: October 20, 2016Date of Patent: November 21, 2017Assignee: ARM LimitedInventors: James Dennis Dodrill, Amanda Ashley Scantlin
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Patent number: 9823298Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.Type: GrantFiled: August 12, 2015Date of Patent: November 21, 2017Assignee: ARM LimitedInventors: Satheesh Balasubramanian, Shardendu Shekhar, James Dennis Dodrill, Sainarayanan Karatholuvu Suryanarayanan
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Publication number: 20170185709Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Marlin Wayne FREDERICK, JR., Karen Lee DELK, Lena AHLEN, James Dennis DODRILL
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Patent number: 9690889Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.Type: GrantFiled: August 18, 2016Date of Patent: June 27, 2017Assignee: ARM LimitedInventors: Marlin Wayne Frederick, Jr., Karen Lee Delk, Lena Ahlen, James Dennis Dodrill
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Patent number: 9651620Abstract: A measurement circuit and method is provided for generating an oscillating output signal used to derive timing information. The measurement circuit includes a ring oscillator having a plurality of unit cells, where each unit cell comprises at least a storage element whose output signal is used to determine a clock input signal for an adjacent unit cell within the ring oscillator. Control circuitry performs a control operation to control either a set function or a reset function of the storage element in each of the unit cells, in dependence on set or reset signals input to the control circuitry. Oscillation initiation circuitry is used to assert a clock input signal to the storage element in a first unit cell in order to initiate generation of the oscillating output signal, and the control circuitry then performs the control operation in order to control a value of the output signal of the storage element in each unit cell so as to cause the oscillating output signal to be maintained.Type: GrantFiled: November 3, 2014Date of Patent: May 16, 2017Assignee: ARM LimitedInventors: Ramesh Manohar, James Dennis Dodrill
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Publication number: 20170117022Abstract: Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.Type: ApplicationFiled: January 9, 2017Publication date: April 27, 2017Inventors: Yew Keong Chong, Andy Wangkun Chen, Sriram Thyagarajan, Gus Yeung, James Dennis Dodrill
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Publication number: 20170045576Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.Type: ApplicationFiled: August 12, 2015Publication date: February 16, 2017Inventors: Satheesh Balasubramanian, Shardendu Shekhar, James Dennis Dodrill, Sainarayanan Karatholuvu Suryanarayanan
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Publication number: 20160357894Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.Type: ApplicationFiled: August 18, 2016Publication date: December 8, 2016Inventors: Marlin Wayne FREDERICK, JR., Karen Lee DELK, Lena AHLEN, James Dennis DODRILL
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Patent number: 9479147Abstract: A synchronizer flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node.Type: GrantFiled: November 3, 2014Date of Patent: October 25, 2016Assignee: ARM LimitedInventors: Satheesh Balasubramanian, James Dennis Dodrill
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Publication number: 20160124045Abstract: A measurement circuit and method is provided for generating an oscillating output signal used to derive timing information. The measurement circuit includes a ring oscillator having a plurality of unit cells, where each unit cell comprises at least a storage element whose output signal is used to determine a clock input signal for an adjacent unit cell within the ring oscillator. Control circuitry performs a control operation to control either a set function or a reset function of the storage element in each of the unit cells, in dependence on set or reset signals input to the control circuitry. Oscillation initiation circuitry is used to assert a clock input signal to the storage element in a first unit cell in order to initiate generation of the oscillating output signal, and the control circuitry then performs the control operation in order to control a value of the output signal of the storage element in each unit cell so as to cause the oscillating output signal to be maintained.Type: ApplicationFiled: November 3, 2014Publication date: May 5, 2016Inventors: Ramesh MANOHAR, James Dennis Dodrill