Abstract: In order to reduce data storage and transmission bandwidth requirements, a high resolution gray scale image is represented in two separate image forms, namely, a high resolution, high sampling density black and white image and a lower resolution, lower sampling density gray scale image. Generating separate black and white and gray scale image data allows the use of either image form independently. The high resolution black and white image data and the low resolution gray scale image data may be recombined subsequently to produce reconstructed high resolution gray scale image data representing the image.

Abstract: Documents, such as bank checks, are processed at a high rate of speed on an image processing system which optically scans the documents and converts optically perceptible data on the documents into video image data. The video image data from the scanner is compressed by data compression techniques and the compressed data is sent over a high speed data channel to a high speed mass storage device which receives and temporarily stores the data. A lower speed mass data storage device, such as an optical disk, is connected for receiving at a lower data transfer rate the compressed video image data and for storing the video image data for subsequent retrieval. The system also includes real-time quality control systems for monitoring the quality of the image data to detect the existence of unacceptable image quality data and for generating a signal which can be used for immediately stopping the generation of unacceptable quality image data.

Abstract: This specification describes a charge-transfer device transversal filter chip in which an input signal is fed in parallel into a number of channels the outputs of which are summed together to provide the desired transversal filter transfer function. Each channel contains an analog shift register, a signal splitter and a polarity selector. The shift registers are of unequal length to provide a different delay thru each channel. The signal splitter provides a plurality of signal paths thru each channel while the polarity selector determines whether a given path in a given channel is added or subtracted in the summation to determine the gain of the given channel in the summation.

Abstract: A charge transfer device capacitive ratio voltage multiplication circuit has been devised which solves the problem of cumulative DC bias offset by adding a DC signal compensation branch to prevent the accumulation of DC offset potential. The circuit can be expanded to form a weighted sum of multiple inputs which does not incur any corresponding DC bias offset, by making the sum of the characteristic capacitances of each of the multiple inputs equal to the characteristic capacitance of the output portion of the charge transfer device circuit. The circuit allows arithmetic operations to be performed on input signals solely in the charge domain without the necessity of converting charge to voltage to charge, thereby avoiding losses, distortions, offsets and a reduction in dynamic range which would otherwise result.