Abstract: A statistical power indication monitor including a random pattern generator that generates random sample assertions of a sample signal, a total counter that counts a total number of the random sample assertions within a sample time interval, detect logic that provides a detection signal for each power indication signal that is asserted coincident with the sample signal, and counter logic that counts a number of assertions of each detection signal during the sample time interval. The assertion count of each power indication signal divided by the total count provides a statistical indication of power consumption of a corresponding system. A user may use the statistical monitoring information to adjust system or application operation. The random pattern generator may be a pseudo-random pattern generator including a linear feedback shift register and may have programmable seed and sample rate.

Abstract: A method embodiment of the present disclosure includes receiving a delay value associated with an interconnect delay that is measured across interconnect circuitry communicatively coupling a host semiconductor device with a semiconductor device. The method also includes delaying a local clock signal by an amount of delay indicated by the delay value to produce a delayed local clock signal. The method also includes receiving a delayed source clock signal, where the delayed source clock signal is received from the host semiconductor device via the interconnect circuitry. The method also includes outputting a master clock signal based on a comparison of the delayed source clock signal and the delayed local clock signal, where the master clock signal is utilized to generate one or more aligned clock signals on the semiconductor device that are aligned with a source clock signal generated on the host semiconductor device.

Abstract: A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock. The second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees.

Abstract: A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock. The second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees.

Abstract: A statistical power indication monitor including a random pattern generator that generates random sample assertions of a sample signal, a total counter that counts a total number of the random sample assertions within a sample time interval, detect logic that provides a detection signal for each power indication signal that is asserted coincident with the sample signal, and counter logic that counts a number of assertions of each detection signal during the sample time interval. The assertion count of each power indication signal divided by the total count provides a statistical indication of power consumption of a corresponding system. A user may use the statistical monitoring information to adjust system or application operation. The random pattern generator may be a pseudo-random pattern generator including a linear feedback shift register and may have programmable seed and sample rate.

Abstract: A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock. The second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees.

Abstract: A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock. The second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees.

Abstract: A method and circuit includes providing at least one conductor for receiving an input signal. A termination circuit and a clamp circuit are coupled to the at least one conductor. The termination circuit is enabled while the clamp circuit remains enabled. The clamp circuit is disabled. After disabling the clamp circuit, while the termination circuit remains enabled, both a first differential comparator and a second differential comparator are enabled. The first differential comparator receives a first differential input signal at a first input and a second differential input signal at a second input. The second differential comparator detects when a difference between the first differential input signal and the second differential input signal is greater than a predetermined value and enables transfer of an output of the first differential comparator to a memory controller.

Abstract: A method and circuit includes providing at least one conductor for receiving an input signal. A termination circuit and a clamp circuit are coupled to the at least one conductor. The termination circuit is enabled while the clamp circuit remains enabled. The clamp circuit is disabled. After disabling the clamp circuit, while the termination circuit remains enabled, both a first differential comparator and a second differential comparator are enabled. The first differential comparator receives a first differential input signal at a first input and a second differential input signal at a second input. The second differential comparator detects when a difference between the first differential input signal and the second differential input signal is greater than a predetermined value and enables transfer of an output of the first differential comparator to a memory controller.

Abstract: An external bus master (205) accesses a DRAM (207) using a memory controller (804) internal to a data processor (3) without the use of external multiplexers or any other external circuitry. The need for external multiplexers and even a dedicated integrated circuit pin for providing external control during external master initiated DRAM accesses is removed by the implementation of a circuit and technique for multiplexing row and column addresses of the DRAM internally within the data processor.

Abstract: A system bus controller (103) within a processor (101) includes programmable logic for different modes of chip enable signals on a per-address-space basis. This allows for a "glueless" interface (107) between the processor (101) and different types of external devices (111, 112, 113), such as memory devices. A chip select register value 604, 608, 612 is preprogrammed with respect to each external device coupled to the processor (101). This preprogrammed register value 604, 608, 612 is used by the system bus controller (103) to uniquely configure a read/write access signal to be sent to each of the external devices (111, 112, 113).

Abstract: Control over bus arbitration within a data processing system between a plurality of bus devices (101, 102) coupled by a bus (103) is performed in a user programmable manner by implementing logic circuitry that is responsive to a user programmable bit within a register (203) so that when the bit is asserted, the bus device (102) is able to maintain control over access to the external bus (103). Such a technique is useful for permitting a processor (201) to maintain mastership of an external bus (103) with respect to a direct memory access device (101) also coupled to the bus (103).

Abstract: A user may program a data processor (3) such that external master chip select accesses can be either the same or different length of time than an internal master access through the use of a control register (810). Additionally, the user can turn off the internal transfer acknowledge logic and add external transfer acknowledge logic while still using the internal chip select and write enable generation logic (8) of the data processor. This feature is user programmable on a chip select basis and provides a flexible solution which allows the user to compensate for different external master accesses without requiring external chip select and write enable logic. Therefore, overhead is conserved and efficiency is increased.

Abstract: A method and apparatus for controlling a bus within a data processing system has a first control bit (SAS*), and second control bit (CLA*), and at least one termination signal (TA*, TRA*, TEA*). The CLA* signal is an input to a primary master (10). The primary master (10) provides a base address external to the primary master (10) so that a slave device can access the base address. The CLA* signal is asserted by the slave device to signal that the base address is to be cycled in a bit-wise circular fashion to provide a plurality of addresses out from the primary master (10) wherein each address in the plurality is derived from the base address internal to the primary master (10). Typically four addresses are provided per base address via the internal control of the primary master (10) in response to three sequential assertions of the CLA* signal.

Abstract: A data processor (10) has a single test controller (11). The test controller (11) has a test pattern generator portion (26) and a memory verification element (27). The test pattern generator (26) generates and communicates a plurality of test patterns to the plurality of memories (12, 13, and 14) through a second storage device (17). A first storage device (16) is used to store data read from the plurality of memories (12, 13, and 14). The data from the first storage device is selectively accessed by the memory verification element (27) via the bus (31). A bit (32) or more than one bit is used to communicate to external to the processor (10) whether the memories (12, 13, and 14) are operating in an error free manner.

Abstract: A method and apparatus for controlling a bus within a data processing system has a first control bit (SAS*), a second control bit (CLA*), and at least one termination signal (TA*, TRA*, TEA*). The termination signals cannot usually be provided as a valid signal for every clock edge of the apparatus when the apparatus is operating at a high frequency. Therefore, within in the apparatus, the termination signals are not always sampled at every clock edge. Instead, there is at least one counter within the primary master (10) which delays the sampling of the termination bits for a predetermined number of clocks cycles to allow time for the termination signals to settle and become valid logic signals before sampling begins. The SAS* signal communicates, external to the primary master (10), whether the sampling of the termination bits is being performed, or the sampling of the termination bits is being suppressed.

Abstract: A bus protocol uses signals to designate a bus transfer termination (BTT*) and a bus grant relinquish (BGR*). The BTT* signal is an output which is asserted by a bus master which currently has ownership of a bus to indicate to other potential bus masters that a bus transfer is complete and that bus ownership may be transferred to another bus master. The BGR* signal is an input to a bus master. When BGR* is asserted, a bus arbiter/controller is informing the current bus master that the bus must be relinquished as soon as possible, after the deassertion of the Bus Grant signal, with no regard for locked sequences. If BGR* is deasserted, the bus arbiter is informing the current bus master that the bus can be relinquished at a time which is convenient for the current bus master. In general, BGR* is a bit which indicates the urgency of a pending bus ownership transfer.

Abstract: A data processing system receives a CLK signal for performing operations internal to a data processor (10). The data processor (10) has a CPU (12) which performs operations in response to the CLK signal. The bus is allowed to operate at a frequency which is less than or equal to the operational frequency of the CLK. The bus clock is typically either equal to the clock in frequency or runs at one-half or one-quarter speed. A CLKEN* signal input to the processor (10) is asserted to indicate an active edge of the external bus clock and synchronize the active edge of the external bus clock with an active edge of CLK to allow an active edge of CLK to perform bus operations which coincide with the active edge of the external bus clock. In another form, an internal counter/control circuit (20) may be used internal to the processor (10) to generate internal CLKEN* signals.

Abstract: An integrated circuit implements an on chip thermal circuit (12) for measuring temperature of an operating integrated circuit die (10) by requiring only one dedicated integrated circuit pin (16). A second integrated circuit pin (18) is utilized but is also connected directly connected to other circuitry (14) on the integrated circuit and is used by the other circuitry at the same time that the integrated circuit die temperature is being measured. In one form, the second integrated circuit pin is a ground terminal. Error voltages coupled to the ground terminal may be removed from the temperature calculation by an external differential amplifier (24).

Abstract: A method and apparatus for placing a data processor (12) into a low-power mode of operation using a system (10). The system (10) has a processor (12). The processor (12) has access to a bus (18). The bus (18) is coupled to a bus controller (14). The processor (12) sends a broadcast cycle out through the bus (18) when the processor (12) desires to enter a low-power mode of operation. The bus controller (14) determines that the broadcast cycle has been sent on the bus (18). The bus controller (14) waits a predetermined amount of time to process the low-power request and grants permission to the processor (12) to enter the low-power mode via the communication of a transmission termination signal. The processor (12) conditionally drives either logic ones or a tri-state value onto the bus (18) depending upon whether or not the processor (12) has been granted ownership of the bus (18).