Abstract: A more computationally efficient and scalable systolic architecture is provided for computing the discrete Fourier transform. The systolic architecture also provides a method for reducing the array area by limiting the number of complex multipliers. In one embodiment, the design improvement is achieved by taking advantage of a more efficient computation scheme based on symmetries in the Fourier transform coefficient matrix and the radix-4 butterfly. The resulting design provides an array comprised of a plurality of smaller base-4 matrices that can simply be added or removed to provide scalability of the design for applications involving different transform lengths to be calculated. In this embodiment, the systolic array size provides greater flexibility because it can be applied for use with any transform length which is an integer multiple of sixteen.

Abstract: The present invention provides a more computationally efficient and scalable systolic architecture for computing the discrete Fourier transform. The systolic architecture also provides a method for reducing the array area by limiting the number of complex multipliers. In one preferred embodiment, the design improvement is achieved by taking advantage of a more efficient computation scheme based on symmetries in the Fourier transform coefficient matrix and the radix-4 butterfly. The resulting design provides an array comprised of a plurality of smaller base-4 matrices that can simply be added or removed to provide scalability of the design for applications involving different transform lengths to be calculated. In this embodiment, the systolic array size provides greater flexibility because it can be applied for use with any transform length which is an integer multiple of sixteen.

Abstract: A cellular array processor (10) for efficiently performing data dependent processing such as floating point arithmetic functions. One module (84) in the array processor (12) generates a signal applied to bus line (24) when all of the bits in a register (86) are zero. The signal on bus line (24) effects the shifting operation of a shift register (36) in a memory module (34) located on a different functional plane. Thus, the processing functions carried out in each elemental processor (26) can be made to depend on the value of data stored therein instead of being dictated solely by a simultaneous executed instruction from the control processor (14) as is the normal case.

Abstract: A computer architecture 10 for performing iconic and symbolic operations on image data is disclosed. Three levels of processing elements (CAAPP, ICP, GPPA) are disclosed. The processing elements in the lowest level (CAAPP) are provided with a plurality of controllable gates (N, S, E, W, H, V, NW, NE) that are used to selectively connect together processing elements in that level. In such manner, certain algorithms such as the minimum spanning tree algorithm can be efficiently performed.

Abstract: A digital integrated circuit that includes on a common substrate both charge-coupled device (CCD) circuitry and metal-oxide semiconductor (MOS) circuitry that combine together efficiently to implement a complex digital function such as a multi-bit multiplier or divider. The CCD circuitry includes an array of full adder cells and the MOS circuitry selectively processes and channels certain bits of a plurality of digital input bits to the individual full adder cells, such processing being based on other of the digital input bits. The introduction of MOS logic into the CCD circuit permits greater flexibility in the layout and interconnection of the individual full adder cells and permits the utilization of more efficient algorithms than otherwise could be used in circuits having CCD elements alone.

Abstract: A computer architecture is disclosed for analyzing automatic image understanding problems. The architecture is designed so that it can efficiently perform a wide spectrum of tasks ranging from low level or iconic processing to high level or symbolic processing tasks. A first level (12) of image processing elements is provided for operating on the image matrix on a pixel per processing element basis. A second level (14) of processing elements is provided for operating on a plurality of pixels associated with a given array of first level processing elements. A third level (16) of processing elements is designed to instruct the first and second level processing elements, as well as for operating on a larger segment of the matrix. A host computer (18) is provided that directly communicates with at least each third level processing element. A high degree of parallelism is provided so that information can be readily transferred within the architecture at high speeds.

Abstract: A ripple adder is implemented as a charge coupled device in such a manner that each carry bit propagates between succeeding full adder stages substantially simultaneously as each stage computes the sum of its two bits, so that the addition in each full adder stage may be carried out in parallel rather than in succession. The i.sup.th one of the CCD full adder stages includes charge transfer means for receiving two bits of charge, namely the i.sup.th bits of the two n-bit words which are to be summed. First and second charge storage means are provided, each having the capacity to store one bit of charge only, so that excess charge will cause an overflow. Means for sensing overflow charge stored in the second charge storage means is connected to a carry bit charge injector in the i.sup.th +1 adder stage.