Abstract: A monitor device and associated methodology are disclosed which provide a self contained, relatively small and continuously wearable package for the monitoring of heart related parameters, including ECG. The detection of heart related parameters is predicated on the location of inequipotential signals located within regions of the human body conventionally defined as equivalent for the purpose of detection of heart related electrical activity, such as on single limbs. Amplification, filtering and processing methods and apparatus are described in conjunction with analytical tools for beat detection and display.

Abstract: An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.

Abstract: Pneumatic compression devices and methods for using the same are disclosed. A pneumatic compression device may include a compression pump, a fill/exhaust valve, a transducer, a plurality of cell valves, and a controller. The compression pump may output a pressurized fluid via an output. The fill/exhaust valve may connect one or more cell valves to the compression pump when in an open state and to the atmosphere when in a closed state. The transducer may sense a pressure level. Each cell valve may correspond to a cell and may connect the fill/exhaust valve to the corresponding cell when in an open state. The controller may determine a state (either open or closed) for each of the fill/exhaust valve and the plurality of cell valves based on at least the pressure level sensed by the transducer.

Abstract: The invention comprises systems, methods, and devices capable of deriving and predicting the occurrence of a number of physiological and conditional states and events based on sensed data. The systems, methods, and devices utilize the predicted and derived states for a number of health and wellness related applications including the administering therapy and providing actionable data for lifestyle and health improvement.

Abstract: A monitor device and associated methodology are disclosed which provide a self contained, relatively small and continuously wearable package for the monitoring of heart related parameters, including ECG. The detection of heart related parameters is predicated on the location of inequipotential signals located within regions of the human body conventionally defined as equivalent for the purpose of detection of heart related electrical activity, such as on single limbs. Amplification, filtering and processing methods and apparatus are described in conjunction with analytical tools for beat detection and display.

Abstract: A monitor device and associated methodology are disclosed which provide a self contained, relatively small and continuously wearable package for the monitoring of heart related parameters, including ECG. The detection of heart related parameters is predicated on the location of inequipotential signals located within regions of the human body conventionally defined as equivalent for the purpose of detection of heart related electrical activity, such as on single limbs. Amplification, filtering and processing methods and apparatus are described in conjunction with analytical tools for beat detection and display.

Abstract: A monitor device and associated methodology are disclosed which provide a self contained, relatively small and continuously wearable package for the monitoring of heart related parameters, including ECG. The detection of heart related parameters is predicated on the location of inequipotential signals located within regions of the human body conventionally defined as equivalent for the purpose of detection of heart related electrical activity, such as on single limbs. Amplification, filtering and processing methods and apparatus are described in conjunction with analytical tools for beat detection and display.

Abstract: A monitor device and associated methodology are disclosed which provide a self contained, relatively small and continuously wearable package for the monitoring of heart related parameters, including ECG. The detection of heart related parameters is predicated on the location of inequipotential signals located within regions of the human body conventionally defined as equivalent for the purpose of detection of heart related electrical activity, such as on single limbs. Amplification, filtering and processing methods and apparatus are described in conjunction with analytical tools for beat detection and display.

Abstract: A monitoring system comprises a module having at least one sensor to determine human status information. The device may be durable or disposable. A receiver may be provided to obtain and display data from the device. The device may also display the output data. The output data comprises both detected and derived data relating to physiological and contextual parameters of the wearer and may be transmitted directly to a local recipient or remotely over a communications network. The system is capable of deriving and predicting the occurrence of a number of physiological and conditional states and events and reporting the same as output data.

Abstract: The invention comprises systems, methods, and devices capable of deriving and predicting the occurrence of a number of physiological and conditional states and events based on sensed data. The systems, methods, and devices utilize the predicted and derived states for a number of health and wellness related applications including the administering therapy and providing actionable data for lifestyle and health improvement.

Abstract: The invention comprises systems, methods, and devices capable of deriving and predicting the occurrence of a number of physiological and conditional states and events based on sensed data. The systems, methods, and devices utilize the predicted and derived states for a number of health and wellness related applications including the administering therapy and providing actionable data for lifestyle and health improvement.

Abstract: The invention comprises systems, methods, and devices capable of deriving and predicting the occurrence of a number of physiological and conditional states and events based on sensed data. The systems, methods, and devices utilize the predicted and derived states for a number of health and wellness related applications including the administering therapy and providing actionable data for lifestyle and health improvement.

Abstract: A monitor device and associated methodology are disclosed which provide a self contained, relatively small and continuously wearable package for the monitoring of heart related parameters, including ECG. The detection of heart related parameters is predicated on the location of inequipotential signals located within regions of the human body conventionally defined as equivalent for the purpose of detection of heart related electrical activity, such as on single limbs. Amplification, filtering and processing methods and apparatus are described in conjunction with analytical tools for beat detection and display.

Abstract: An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.

Abstract: An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.

Abstract: A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.

Abstract: An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.

Abstract: An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.

Abstract: A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master device via the first bus and to transmit signals to the one or more slave devices via the second bus in response to the incoming signals, and a read buffer to receive outgoing signals from the one or more slave devices via the second bus and to transmit signals to the master device via the first bus in response to the outgoing signals.

Abstract: A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.